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rev. 4126f?can?12/03 features 80c51 core architecture 256 bytes of on-chip ram 256 bytes of on-chip xram 16k bytes of on-chip flash memory ? data retention: 10 years at 85c ? erase/write cycle: 100k 2k bytes of on-chip flash for bootloader 2k bytes of on-chip eeprom ? erase/write cycle: 100k 14-sources 4-level interrupts three 16-bit timers/counters full duplex uart compatible 80c51 maximum crystal frequency 40 mhz. in x2 mode, 20 mhz (cpu core, 40 mhz) three or four ports: 16 or 20 digital i/o lines two-channel 16-bit pca ? pwm (8-bit) ? high-speed output ? timer and edge capture double data pointer 21-bit watchdog timer (7 programmable bits) a 10-bit resolution analog-to-digital converter (adc) with 8 multiplexed inputs full can controller ? fully compliant with can rev.# 2.0a and 2.0b ? optimized structure for communication management (via sfr) ? 4 independent message objects -each message object programmable on transmission or reception -individual tag and mask filters up to 29-bit identifier/channel -8-byte cyclic data register (fifo)/message object -16-bit status and control register/message object -16-bit time-stamping register/message object -can specification 2.0 part a or 2.0 part b programmable for each message object -access to message object control and data registers via sfr -programmable reception buffer length up to 4 message objects -priority management of reception of hits on several message objects simultaneously (basic can feature) -priority management for transmission -message object overrun interrupt ? supports -time triggered communication -autobaud and listening mode -programmable automatic reply mode 1-mbit/s maximum transfer rate at 8 mhz (1) crystal frequency in x2 mode readable error counters programmable link to on-chip timer for time stamping and network synchronization independent baud rate prescaler data, remote, error and overload frame handling power-saving modes ? idle mode ? power-down mode power supply: 3 volts to 5.5 volts temperature range: industrial (-40 to +85 c) packages: soic28, soic24, plcc28, vqfp32 note: 1. at brp = 1 sampling point will be fixed. enhanced 8-bit microcontroller with can controller and flash T89C51CC02
2 T89C51CC02 4126f?can?12/03 description part of the canary tm family of 8-bit microcontrollers dedicated to can network applica- tions, the T89C51CC02 is a low-pin count 8-bit flash microcontroller. in x2 mode a maximum external clock rate of 20 mhz reaches a 300 ns cycle time. besides the full can controller T89C51CC02 provides 16k bytes of flash memory including in-system programming (isp), 2k bytes boot flash memory, 2k bytes eeprom and 512 bytes ram. special attention is payed to the reduction of the electro-magnetic emission of T89C51CC02. block diagram note: 1. 8 analog inputs/8 digital i/o. 2. 2-bit i/o port. timer 0 int ram 256x8 t0 t1 rxd txd xtal2 xtal1 uart cpu timer 1 int1 ctrl int0 c51 core p2 (2) port 1 port 2 port 3 parallel i/o ports p1 (1) p3 xram 256 x 8 ib-bus pca reset watch dog pca eci vss vcc timer 2 t2ex t2 port 4 p4 (2) 10-bit adc flash 16k x 8 boot loader 2k x 8 ee prom 2k x 8 can controller txdc rxdc vavcc varef vagnd
3 T89C51CC02 4126f?can?12/03 pin configurations p3.4/t0 p3.3/int1 p4.1/rxdc 1 p3.7 p3.2/int0 p1.5/an5 p1.7/an7 p1.6/an6 p2.0 varef vavcc vagnd p1.0/ an0/t2 p1.1/an1/t2ex p1.2/an2/eci p1.3/an3/cex0 p1.4/an4/cex1 2 3 4 5 6 7 8 9 10 11 12 28 27 26 25 24 23 22 21 20 19 18 17 rese t vcc vss p4.0/txdc p2.1 p3.6 p3.5/t1 p3.1/txd 13 p3.0/rxd 14 16 xtal1 15 xtal2 so28 p1.3/an3/cex0 p1.2/an2/eci p1.1/an1/t2ex p1.0/an 0/t2 varef vagnd reset vss vcc xtal1 xtal2 p3.7 p4.0/txdc p4.1/rxdc p2.1 p3.6 25 24 23 22 21 20 19 5 6 7 8 9 10 11 12 13 14 15 16 17 18 4 3 2 p2.0 p1.4/an4/cex1 p1.5/an5 p1.6/an6 p1.7/an7 p3.0/rxd p3.1/txd p3.2/int0 p3.3/int1 p3.4/t0 p3.5/t1 1 28 27 26 vavcc plcc-28 p3.1/txd p3.0/rxd p4.1/rxdc 1 p3.4/t0 xtal2 p1.5/an5 p1.7/an7 p1.6/an6 rese t varef vavcc vagnd p1.0/ an0/t2 p1.1/an1/t2ex p1.2/an2/eci p1.3/an3/cex0 p1.4/an4/cex1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 vss xtal1 vcc p4.0/txdc p3.5/t1 p3.3/int1 p3.2/int0 so24
4 T89C51CC02 4126f?can?12/03 p1.3/an3/cex0 p1.2/an2/eci p1.1/an1/t2ex p1.0/an 0/t2 varef vagnd reset vss vcc xtal1 xtal2 p3.7 p4.0/txdc p4.1/rxdc p2.1 p3.6 p2.0 p1.4/an4/cex1 p1.5/an5 p1.6/an6 p1.7/an7 p3.0/rxd p3.1/txd p3.2/int0 p3.3/int1 p3.4/t0 p3.5/t1 vavcc qfp-32 nc nc nc nc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 23 24 25 26 27 28 29 30 31 32 22
5 T89C51CC02 4126f?can?12/03 pin description pin name type description vss gnd circuit ground vcc supply voltage varef reference voltage for adc (input) vavcc supply voltage for adc vagnd reference ground for adc (internaly connected with the vss) p1.0:7 i/o port 1: is an 8-bit bi-directional i/o port with internal pull-ups. port 1 pins can be used for digital input/output or as analog inputs for the analog digital converter (adc). port 1 pins that have 1?s written to them are pulled high by the internal pull-up transistors and can be used as inputs in this state. as inputs, port 1 pins that are being pulled low externally will be the source of current (i il , see section ?electrical characteristic?) because of the internal pull-ups. port 1 pins are assigned to be used as analog inputs via the adccf register (in this case the internal pull-ups are disconnected). as a secondary digital function, port 1 contains the timer 2 external trigger and clock input; the pca external clock input and the pca module i/o. p1.0/an0/t2 analog input channel 0, external clock input for timer/counter2. p1.1/an1/t2ex analog input channel 1, trigger input for timer/counter2. p1.2/an2/eci analog input channel 2, pca external clock input. p1.3/an3/cex0 analog input channel 3, pca module 0 entry of input/pwm output. p1.4/an4/cex1 analog input channel 4, pca module 1 entry of input/pwm output. p1.5/an5 analog input channel 5, p1.6/an6 analog input channel 6, p1.7/an7 analog input channel 7, it can drive cmos inputs without external pull-ups. p2.0:1 i/o port 2: is an 2-bit bi-directional i/o port with internal pull-ups. port 2 pins that have 1?s written to them are pulled high by the internal pull-ups and can be used as inputs in this state. as inputs, port 2 pins that are being pulled low externally will be a source of current (iil, on the datasheet) because of the internal pull-ups. in the T89C51CC02 port 2 can sink or source 5ma. it can drive cmos inputs without external pull-ups.
6 T89C51CC02 4126f?can?12/03 p3.0:7 i/o port 3: is an 8-bit bi-directional i/o port with internal pull-ups. port 3 pins that have 1?s written to them are pulled high by the internal pull-up transistors and can be used as inputs in this state. as inputs, port 3 pins that are being pulled low externally will be a source of current (i il , see section ?electrical characteristic?) because of the internal pull-ups. the output latch corresponding to a secondary function must be programmed to one for that function to operate (except for txd and wr ). the secondary functions are assigned to the pins of port 3 as follows: p3.0/rxd: receiver data input (asynchronous) or data input/output (synchronous) of the serial interface p3.1/txd: transmitter data output (asynchronous) or clock output (synchronous) of the serial interface p3.2/int0 : external interrupt 0 input/timer 0 gate control input p3.3/int1 : external interrupt 1 input/timer 1 gate control input p3.4/t0: timer 0 counter input p3.5/t1: timer 1 counter input p3.6: regular i/o port pin p3.7: regular i/o port pin p4.0:1 i/o port 4: is an 2-bit bi-directional i/o port with internal pull-ups. port 4 pins that have 1?s written to them are pulled high by the internal pull-ups and can be used as inputs in this state. as inputs, port 4 pins that are being pulled low externally will be a source of current (iil, on the datasheet) because of the internal pull-up transistor. the output latch corresponding to a secondary function rxdc must be programmed to one for that function to operate. the secondary functions are assigned to the two pins of port 4 as follows: p4.0/txdc: transmitter output of can controller p4.1/rxdc: receiver input of can controller. it can drive cmos inputs without external pull-ups. reset i/o reset: a high level on this pin during two machine cycles while the oscillator is running resets the device. an internal pull-down resistor to vss permits power-on reset using only an external capacitor to vcc. xtal1 i xtal1: input of the inverting oscillator amplifier and input of the internal clock generator circuits. to drive the device from an external clock source, xtal1 should be driven, while xtal2 is left unconnected. to operate above a frequency of 16 mhz, a duty cycle of 50% should be maintained. xtal2 o xtal2: output from the inverting oscillator amplifier. pin name type description
7 T89C51CC02 4126f?can?12/03 i/o configurations each port sfr operates via type-d latches, as illustrated in figure 1 for ports 3 and 4. a cpu ?write to latch? signal initiates transfer of internal bus data into the type-d latch. a cpu ?read latch? signal transfers the latched q output onto the internal bus. similarly, a ?read pin? signal transfers the logical level of the port pin. some port data instructions activate the ?read latch? signal while others activate the ?read pin? signal. latch instruc- tions are referred to as read-modify-write instructions. each i/o line may be independently programmed as input or output. port structure figure 1 shows the structure of ports, which have internal pull-ups. an external source can pull the pin low. each port pin can be configured either for general-purpose i/o or for its alternate input output function. to use a pin for general-purpose output, set or clear the corresponding bit in the px reg- ister (x = 1 to 4). to use a pin for general-purpose input, set the bit in the px register. this turns off the output fet drive. to configure a pin for its alternate function, set the bit in the px register. when the latch is set, the ?alternate output function? signal controls the output level (see figure 1). the operation of ports is discussed further in ?quasi-bi-directional port operation? paragraph. figure 1. ports structure note: 1. the internal pull-up can be disabled on p1 when analog function is selected. d cl q latch internal write to latch read pin read latch alternate output function vcc internal pull-up (1) alternate input function bus p2.x p3.x p4.x p1.x (1)
8 T89C51CC02 4126f?can?12/03 read-modify-write instructions some instructions read the latch data rather than the pin data. the latch based instruc- tions read the data, modify the data and then rewrite the latch. these are called ?read- modify-write? instructions. below is a complete list of these special instructions (see table 1). when the destination operand is a port or a port bit, these instructions read the latch rather than the pin: it is not obvious that the last three instructions in this list are read-modify-write instruc- tions. these instructions read the port (all 8 bits), modify the specifically addressed bit and write the new byte back to the latch. these read-modify-write instructions are directed to the latch rather than the pin in order to avoid possible misinterpretation of voltage (and therefore, logic) levels at the pin. for example, a port bit used to drive the base of an external bipolar transistor cannot rise above the transistor?s base-emitter junction voltage (a value lower than vil). with a logic one written to the bit, attempts by the cpu to read the port at the pin are misinterpreted as logic zero. a read of the latch rather than the pins returns the correct logic one value. quasi bi-directional port operation port 1, port 3 and port 4 have fixed internal pull-ups and are referred to as ?quasi-bidi- rectional? ports. when configured as an input, the pin impedance appears as logic one and sources current in response to an external logic zero condition. resets write logic one to all port latches. if logical zero is subsequently written to a port latch, it can be returned to input conditions by a logic one written to the latch. note: port latch values change near the end of read-modify-write insruction cycles. output buffers (and therefore the pin state) are updated early in the instruction after read-mod- ify-write instruction cycle. logical zero-to-one transitions in port 1, port 3 and port 4 use an additional pull-up (p1) to aid this logic transition see figure 2. this increases switch speed. this extra pull-up sources 100 times normal internal circuit current during 2 oscillator clock periods. the internal pull-ups are field-effect transistors rather than linear resistors. pull-ups consist of three p-channel fet (pfet) devices. a pfet is on when the gate senses logic zero and off when the gate senses logic one. pfet #1 is turned on for two oscillator periods immediately after a zero-to-one transition in the port latch. a logic one at the port pin turns on pfet #3 (a weak pull-up) through the inverter. this inverter and pfet pair form a latch to drive logic one. pfet #2 is a very weak pull-up switched on whenever the table 1. read/modify/write instructions instruction description example anl logical and anl p1, a orl logical or orl p2, a xrl logical ex-or xrl p3, a jbc jump if bit = 1 and clear bit jbc p1.1, label cpl complement bit cpl p3.0 inc increment inc p2 dec decrement dec p2 djnz decrement and jump if not zero djnz p3, label mov px.y, c move carry bit to bit y of port x mov p1.5, c clr px.y clear bit y of port x clr p2.4 set px.y set bit y of port x set p3.3
9 T89C51CC02 4126f?can?12/03 associated nfet is switched off. this is traditional cmos switch convention. current strengths are 1/10 that of pfet #3. note: during reset, pfet#1 is not avtivated. during reset, only the weak pfet#3 pull up the pin. figure 2. internal pull-up configurations read pin input data p1.x output data 2 osc. periods n p1(1) p2 p3 vcc vcc vcc p2.x p3.x p4.x
10 T89C51CC02 4126f?can?12/03 sfr mapping tables 3 through table 11 show the special function registers (sfrs) of the T89C51CC02. table 2. c51 core sfrs mnemonicaddname 76543210 acc e0h accumulator b f0h b register psw d0h program status word cy ac f0 rs1 rs0 ov f1 p sp 81h stack pointer dpl 82h data pointer low byte lsb of dptr dph 83h data pointer high byte msb of dptr table 3. i/o port sfrs mnemonicaddname 76543210 p1 90h port 1 p2 a0h port 2 (x2) p3 b0h port 3 p4 c0h port 4 (x2) table 4. timers sfrs mnemonicaddname 76543210 th0 8ch timer/counter 0 high byte tl0 8ah timer/counter 0 low byte th1 8dh timer/counter 1 high byte tl1 8bh timer/counter 1 low byte th2 cdh timer/counter 2 high byte tl2 cch timer/counter 2 low byte tcon 88h timer/counter 0 and 1 control tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 tmod 89h timer/counter 0 and 1 modes gate1 c/t1# m11 m01 gate0 c/t0# m10 m00
11 T89C51CC02 4126f?can?12/03 t2con c8h timer/counter 2 control tf2 exf2 rclk tclk exen2 tr2 c/t2# cp/rl2# t2mod c9h timer/counter 2 mode t2oe dcen rcap2h cbh timer/counter 2 reload/capture high byte rcap2l cah timer/counter 2 reload/capture low byte wdtrst a6h watchdog timer reset wdtprg a7h watchdog timer program s2 s1 s0 table 4. timers sfrs (continued) mnemonicaddname 76543210 table 5. serial i/o port sfrs mnemonicaddname 76543210 scon 98h serial control fe/sm0 sm1 sm2 ren tb8 rb8 ti ri sbuf 99h serial data buffer saden b9h slave address mask saddr a9h slave address table 6. pca sfrs mnemonicaddname 76543210 ccon d8h pca timer/counter control cf cr ccf4 ccf3 ccf2 ccf1 ccf0 cmod d9h pca timer/counter mode cidl cps1 cps0 ecf cl e9h pca timer/counter low byte ch f9h pca timer/counter high byte ccapm0 ccapm1 dah dbh pca timer/counter mode 0 pca timer/counter mode 1 ecom0 ecom1 capp0 capp1 capn0 capn1 mat0 mat1 tog0 tog1 pwm0 pwm1 eccf0 eccf1 ccap0h ccap1h fah fbh pca compare capture module 0 h pca compare capture module 1 h ccap0h7 ccap1h7 ccap0h6 ccap1h6 ccap0h5 ccap1h5 ccap0h4 ccap1h4 ccap0h3 ccap1h3 ccap0h2 ccap1h2 ccap0h1 ccap1h1 ccap0h0 ccap1h0
12 T89C51CC02 4126f?can?12/03 ccap0l ccap1l eah ebh pca compare capture module 0 l pca compare capture module 1 l ccap0l7 ccap1l7 ccap0l6 ccap1l6 ccap0l5 ccap1l5 ccap0l4 ccap1l4 ccap0l3 ccap1l3 ccap0l2 ccap1l2 ccap0l1 ccap1l1 ccap0l0 ccap1l0 table 6. pca sfrs (continued) mnemonicaddname 76543210 table 7. interrupt sfrs mnemonicaddname 76543210 ien0 a8h interrupt enable control 0 ea ec et2 es et1 ex1 et0 ex0 ien1 e8h interrupt enable control 1 etim eadc ecan ipl0 b8h interrupt priority control low 0 ppc pt2 ps pt1 px1 pt0 px0 iph0 b7h interrupt priority control high 0 ppch pt2h psh pt1h px1h pt0h px0h ipl1 f8h interrupt priority control low 1 povrl padcl pcanl iph1 f7h interrupt priority control high1 povrh padch pcanh table 8. adc sfrs mnemonicaddname 76543210 adcon f3h adc control psidle aden adeoc adsst sch2 sch1 sch0 adcf f6h adc configuration ch7 ch6 ch5 ch4 ch3 ch2 ch1 ch0 adclk f2h adc clock prs4 prs3 prs2 prs1 prs0 addh f5h adc data high byte adat9 adat8 adat7 adat6 adat5 adat4 adat3 adat2 addl f4h adc data low byte adat1 adat0 table 9. can sfrs mnemonicaddname 76543210 cangcon abh can general control abrq ovrq ttc syncttc aut-baud test ena gres cangsta aah can general status ovfg tbsy rbsy enfg boff errp cangit 9bh can general interrupt canit ovrtim ovrbuf serg cerg ferg aerg canbt1 b4h can bit timing 1 brp5 brp4 brp3 brp2 brp1 brp0 canbt2 b5h can bit timing 2 sjw1 sjw0 prs2 prs1 prs0 canbt3 b6h can bit timing 3 phs22 phs21 phs20 phs12 phs11 phs10 smp
13 T89C51CC02 4126f?can?12/03 canen cfh can enable channel byte ench3 ench2 ench1 ench0 cangie c1h can general interrupt enable enrx entx enerch enbuf energ canie c3h can interrupt enable channel byte iech3 iech2 iech1 iech0 cansit bbh can status interrupt channel byte sit3 sit2 sit1 sit0 cantcon a1h can timer control tpresc 7 tpresc 6 tpresc 5 tpresc 4 tpresc 3 tpresc 2 tpresc 1 tpresc 0 cantimh adh can timer high cantim 15 cantim 14 cantim 13 cantim 12 cantim 11 cantim 10 cantim 9 cantim 8 cantiml ach can timer low cantim 7 cantim 6 cantim 5 cantim 4 cantim 3 cantim 2 cantim 1 cantim 0 canstmph afh can timer stamp high timstmp 15 timstmp 14 timstmp 13 timstmp 12 timstmp 11 timstmp 10 timstmp 9 timstmp 8 canstmpl aeh can timer stamp low timstmp7 timstmp 6 timstmp 5 timstmp 4 timstmp 3 timstmp 2 timstmp 1 timstmp 0 canttch a5h can timer ttc high timttc 15 timttc 14 timttc 13 timttc 12 timttc 11 timttc 10 timttc 9 timttc 8 canttcl a4h can timer ttc low timttc 7 timttc 6 timttc 5 timttc 4 timttc 3 timttc 2 timttc 1 timttc 0 cantec 9ch can transmit error counter tec7 tec6 tec5 tec4 tec3 tec2 tec1 tec0 canrec 9dh can receive error counter rec7 rec6 rec5 rec4 rec3 rec2 rec1 rec0 canpage b1h can page - - chnb1 chnb0 ainc indx2 indx1 indx0 canstch b2h can status channel dlcw txok rxok berr serr cerr ferr aerr canconch b3h can control channel conch1 conch0 rplv ide dlc3 dlc2 dlc1 dlc0 canmsg a3h can message data msg7 msg6 msg5 msg4 msg3 msg2 msg1 msg0 canidt1 bch can identifier tag byte 1(part a) can identifier tag byte 1(partb) idt10 idt28 idt9 idt27 idt8 idt26 idt7 idt25 idt6 idt24 idt5 idt23 idt4 idt22 idt3 idt21 canidt2 bdh can identifier tag byte 2 (parta) can identifier tag byte 2 (partb) idt2 idt20 idt1 idt19 idt0 idt18 - idt17 - idt16 - idt15 - idt14 - idt13 canidt3 beh can identifier tag byte 3(parta) can identifier tag byte 3(partb) - idt12 - idt11 - idt10 - idt9 - idt8 - idt7 - idt6 - idt5 canidt4 bfh can identifier tag byte 4(parta) can identifier tag byte 4(partb) - idt4 - idt3 - idt2 - idt1 - idt0 rtrtag - rb1tag rb0taf canidm1 c4h can identifier mask byte 1(parta) can identifier mask byte 1(partb) idmsk10 idmsk28 idmsk9 idmsk27 idmsk8 idmsk26 idmsk7 idmsk25 idmsk6 idmsk24 idmsk5 idmsk23 idmsk4 idmsk22 idmsk3 idmsk21 table 9. can sfrs (continued) mnemonicaddname 76543210
14 T89C51CC02 4126f?can?12/03 canidm2 c5h can identifier mask byte 2(parta) can identifier mask byte 2(partb) idmsk2 idmsk20 idmsk1 idmsk19 idmsk0 idmsk18 - idmsk17 - idmsk16 - idmsk15 - idmsk14 - idmsk13 canidm3 c6h can identifier mask byte 3(parta) can identifier mask byte 3(partb) - idmsk12 - idmsk11 - idmsk10 - idmsk9 - idmsk8 - idmsk7 - idmsk6 - idmsk5 canidm4 c7h can identifier mask byte 4(parta) can identifier mask byte 4(partb) - idmsk4 - idmsk3 - idmsk2 - idmsk1 - idmsk0 rtrmsk - idemsk table 9. can sfrs (continued) mnemonicaddname 76543210 table 10. other sfrs mnemonicaddname 76543210 pcon 87h power control smod1 smod0 pof gf1 gf0 pd idl auxr1 a2h auxiliary register 1 enboot gf3 0 dps ckcon 8fh clock control canx2 wdx2 pcax2 six2 t2x2 t1x2 t0x2 x2 fcon d1h flash control fpl3 fpl2 fpl1 fpl0 fps fmod1 fmod0 fbusy eecon d2h eeprom contol eepl3 eepl2 eepl1 eepl0 eee eebusy
15 T89C51CC02 4126f?can?12/03 reserved notes: 1. these registers are bit-addressable. sixteen addresses in the sfr space are both byte-addressable and bit-addressable. the bit-addressable sfrs are those whose address ends in 0 and 8. the bit addresses, in this area, are 0x80 through to 0xff. 2. auxr1 bit enboot is initialized with the content of the bljb bit inverted. table 11. sfr mapping 0/8 (1) 1/9 2/a 3/b 4/c 5/d 6/e 7/f f8h ipl1 xxxx x000 ch 0000 0000 ccap0h 0000 0000 ccap1h 0000 0000 ffh f0h b 0000 0000 adclk xxx0 0000 adcon x000 0000 addl 0000 0000 addh 0000 0000 adcf 0000 0000 iph1 xxxx x000 f7h e8h ien1 xxxx x000 cl 0000 0000 ccap0l 0000 0000 ccap1l 0000 0000 efh e0h acc 0000 0000 e7h d8h ccon 0000 0000 cmod 0xxx x000 ccapm0 x000 0000 ccapm1 x000 0000 dfh d0h psw 0000 0000 fcon 0000 0000 eecon xxxx xx00 d7h c8h t2con 0000 0000 t2mod xxxx xx00 rcap2l 0000 0000 rcap2h 0000 0000 tl2 0000 0000 th2 0000 0000 canen xxxx 0000 cfh c0h p4 xxxx xx11 cangie 1100 0000 canie 1111 0000 canidm1 xxxx xxxx canidm2 xxxx xxxx canidm3 xxxx xxxx canidm4 xxxx xxxx c7h b8h ipl0 x000 0000 saden 0000 0000 cansit xxxx 0000 canidt1 xxxx xxxx canidt2 xxxx xxxx canidt3 xxxx xxxx canidt4 xxxx xxxx bfh b0h p3 1111 1111 canpage 1100 0000 canstch xxxx xxxx canconch xxxx xxxx canbt1 xxxx xxxx canbt2 xxxx xxxx canbt3 xxxx xxxx iph0 x000 0000 b7h a8h ien0 0000 0000 saddr 0000 0000 cangsta 1010 0000 cangcon 0000 0000 cantiml 0000 0000 cantimh 0000 0000 canstmpl xxxx xxxx canstmph xxxx xxxx afh a0h p2 xxxx xx11 cantcon 0000 0000 auxr1 (2) xxxx 00x0 canmsg xxxx xxxx canttcl 0000 0000 canttch 0000 0000 wdtrst 1111 1111 wdtprg xxxx x000 a7h 98h scon 0000 0000 sbuf 0000 0000 cangit 0x00 0000 cantec 0000 0000 canrec 0000 0000 9fh 90h p1 1111 1111 97h 88h tcon 0000 0000 tmod 0000 0000 tl0 0000 0000 tl1 0000 0000 th0 0000 0000 th1 0000 0000 ckcon 0000 0000 8fh 80h sp 0000 0111 dpl 0000 0000 dph 0000 0000 pcon 00x1 0000 87h 0/8 (1) 1/9 2/a 3/b 4/c 5/d 6/e 7/f
16 T89C51CC02 4126f?can?12/03 clock the T89C51CC02 core needs only 6 clock periods per machine cycle. this feature, called ?x2?, provides the following advantages: divides frequency crystals by 2 (cheaper crystals) while keeping the same cpu power. saves power consumption while keeping the same cpu power (oscillator power saving). saves power consumption by dividing dynamic operating frequency by 2 in operating and idle modes. increases cpu power by 2 while keeping the same crystal frequency. in order to keep the original c51 compatibility, a divider-by-2 is inserted between the xtal1 signal and the main clock input of the core (phase generator). this divider may be disabled by the software. an extra feature is available to start after reset in the x2 mode. this feature can be enabled by a bit x2b in the hardware security byte. this bit is described in the section ?in-system programming?. description the x2 bit in the ckcon register (see table 12) allows switching from 12 clock cycles per instruction to 6 clock cycles and vice versa. at reset, the standard speed is activated (std mode). setting this bit activates the x2 feature (x2 mode) for the cpu clock only (see figure 3). the timers 0, 1 and 2, uart, pca, watchdog or can switch in x2 mode only if the corre- sponding bit is cleared in the ckcon register. the clock for the whole circuit and peripheral is first divided by two before being used by the cpu core and peripherals. this allows any cyclic ratio to be accepted on the xtal1 input. in x2 mode, as this divider is by passed, the signals on xtal1 must have a cyclic ratio between 40 to 60%. figure 3. shows the clock generation block diagram. the x2 bit is validated on the xtal1 2 rising edge to avoid glitches when switching from the x2 to the std mode. figure 4 shows the mode switching waveforms.
17 T89C51CC02 4126f?can?12/03 figure 3. clock cpu generation diagram x tal1 x tal2 pd pcon.1 cpu core 1 0 2 periph clock clock peripheral clock symbol cpu clock cpu core clock symbol x2 ckcon.0 x2b hardware byte canx2 ckcon.7 wdx2 ckcon.6 pcax2 ckcon.5 six2 ckcon.4 t2x2 ckcon.3 t1x2 ckcon.2 t0x2 ckcon.1 idl pcon.0 1 0 2 1 0 2 1 0 2 1 0 2 1 0 2 1 0 2 1 0 2 x2 ckcon.0 fcan clock fwd clock fpca clock fuart clock ft2 clock ft1 clock ft0 clock and adc on reset
18 T89C51CC02 4126f?can?12/03 figure 4. mode switching waveforms (1) note: 1. in order to prevent any incorrect operation while operating in the x2 mode, users must be aware that all peripherals usi ng the clock frequency as a time reference (uart, timers...) will have their time reference divided by 2. for example, a free run- ning timer generating an interrupt every 20 ms will then generate an interrupt every 10 ms. a uart with a 4800 baud rate will have a 9600 baud rate. xtal2 xtal1 cpu clock x2 bit x2 mode std mode std mode
19 T89C51CC02 4126f?can?12/03 register table 12. ckcon register ckcon (s:8fh) clock control registe r note: 1. this control bit is validated when the cpu clock bit x2 is set; when x2 is low, this bit has no effect. reset value = 0000 0000b 76543210 canx2 wdx2 pcax2 six2 t2x2 t1x2 t0x2 x2 bit number bit mnemonic description 7canx2 can clock (1) clear to select 6 clock periods per peripheral clock cycle. set to select 12 clock periods per peripheral clock cycle. 6wdx2 watchdog clock (1) clear to select 6 clock periods per peripheral clock cycle. set to select 12 clock periods per peripheral clock cycle. 5 pcax2 programmable counter array clock (1) clear to select 6 clock periods per peripheral clock cycle. set to select 12 clock periods per peripheral clock cycle. 4six2 enhanced uart clock (mode 0 and 2) (1) clear to select 6 clock periods per peripheral clock cycle. set to select 12 clock periods per peripheral clock cycle. 3t2x2 timer 2 clock (1) clear to select 6 clock periods per peripheral clock cycle. set to select 12 clock periods per peripheral clock cycle. 2t1x2 timer 1 clock (1) clear to select 6 clock periods per peripheral clock cycle. set to select 12 clock periods per peripheral clock cycle. 1t0x2 timer 0 clock (1) clear to select 6 clock periods per peripheral clock cycle. set to select 12 clock periods per peripheral clock cycle. 0x2 cpu clock clear to select 12 clock periods per machine cycle (std mode) for cpu and all the peripherals. set to select 6 clock periods per machine cycle (x2 mode) and to enable the individual peripherals ?x2? bits.
20 T89C51CC02 4126f?can?12/03 power management two power reduction modes are implemented in the T89C51CC02: the idle mode and the power-down mode. these modes are detailed in the following sections. in addition to these power reduction modes, the clocks of the core and peripherals can be dynami- cally divided by 2 using the x2 mode detailed in section ?clock?. reset pin in order to start-up (cold reset) or to restart (warm reset) properly the microcontroller, a high level has to be applied on the rst pin. a bad level leads to a wrong initialisation of the internal registers like sfrs, pc, etc. and to unpredictable behavior of the microcon- troller. a warm reset can be applied either directly on the rst pin or indirectly by an internal reset source such as a watchdog, pca, timer, etc. at power-up (cold reset) two conditions are required before enabling a cpu start-up: vdd must reach the specified vdd range, the level on xtal1 input must be outside the specification (vih, vil). if one of these two conditions are not met, the microcontroller does not start correctly and can execute an instruction fetch from anywhere in the program space. an active level applied on the rst pin must be maintained until both of the above conditions are met. a reset is active when the level vih1 is reached and when the pulse width covers the period of time where vdd and the oscillator are not stabilized. two parameters have to be taken into account to determine the reset pulse width: vdd rise time (vddrst), oscillator startup time (oscrst). to determine the capacitor the highest value of these two parameters has to be chosen. the reset circuitry is shown in figure 5. figure 5. reset circuitry table 13 and table 14 give some typical examples for three values of vdd rise times, two values of oscillato r start-up time and two pull-down resistor values. table 13. minimum reset capacitor for a 50k pull-down resistor oscrst/vddrst 1ms 10ms 100ms 5ms 820nf 1.2f 12f 20ms 2.7f 3.9f 12f 0 vdd rrst crst rst pin internal reset reset input circuitry
21 T89C51CC02 4126f?can?12/03 table 14. minimum reset capacitor for a 15k pull-down resistor note: these values assume vdd starts from 0v to the nominal value. if the time between two on/off sequences is too fast, the power-supply decoupling capacitors may not be fully discharged, leading to a bad reset sequence. during a normal operation (warm reset) reset pin must be maintained for at least 2 machine cycles (24 oscillator clock periods) to apply a reset sequence during normal operation. the number of clock periods is mode independent (x2 or x1). watchdog reset a 1k resistor must be added in series with the capacitor to allow the use of watchdog reset pulse output on the rst pin or when an external power-supply supervisor is used. figure 6 shows the reset circuitry when a capacitor is used. figure 6. reset circuitry for a watchdog configuration figure 7 shows the reset circuitry when an external reset circuit is used. figure 7. reset circuitry example using an external reset circuit oscrst/vddrst 1ms 10ms 100ms 5ms 2.7f 4.7f 47f 20ms 10f 15f 47f vdd rrst crst 1k rst pin internal reset watchdog to other on-board circuitry reset input circuitry vdd rrst 1k rst pin internal reset watchdog to other on-board circuitry reset input circuitry rst external reset circuit
22 T89C51CC02 4126f?can?12/03 reset recommendation to prevent flash corruption when a flash program memory is embedded on-chip, it is strongly recommended to use an external reset chip (brown out device) to apply a reset (figure 7). it prevents sys- tem malfunction during periods of insufficient power-supply voltage (power-supply failure, power supply switched off, etc.). idle mode idle mode is a power reduction mode that reduces the power consumption. in this mode, program execution halts. idle mode freezes the clock to the cpu at known states while the peripherals continue to be clocked. the cpu status before entering idle mode is preserved, i.e., the program counter and program status word register retain their data for the duration of idle mode. the contents of the sfrs and ram are also retained. the status of the port pins during idle mode is detailed in table 13. entering idle mode to enter idle mode, set the idl bit in pcon register (see table 15). the T89C51CC02 enters idle mode upon execution of the instruction that sets idl bit. the instruction that sets idl bit is the last instruction executed. note: if idl bit and pd bit are set simultaneously, the T89C51CC02 enters power-down mode. then it does not go in idle mode when exiting power-down mode. exiting idle mode there are two ways to exit idle mode: 1. generate an enabled interrupt. hardware clears idl bit in pcon register which restores the clock to the cpu. exe- cution resumes with the interrupt service routine. upon completion of the interrupt service routine, program execution resumes with the instruction immediately follow- ing the instruction that activated idle mode. the general purpose flags (gf1 and gf0 in pcon register) may be used to indicate whether an interrupt occurred dur- ing normal operation or during idle mode. when idle mode is exited by an interrupt, the interrupt service routine may examine gf1 and gf0. 2. generate a reset. a logic high on the rst pin clears idl bit in pcon register directly and asynchro- nously. this restores the clock to the cpu. program execution momentarily resumes with the instruction immediately following the instruction that activated the idle mode and may continue for a number of clock cycles before the internal reset algorithm takes control. reset initializes the T89C51CC02 and vectors the cpu to address c:0000h. notes: 1. during the time that execution resumes, the internal ram cannot be accessed; how- ever, it is possible for the port pins to be accessed. to avoid unexpected outputs at the port pins, the instruction immediately following the instruction that activated idle mode should not write to a port pin or to the external ram. 2. if idle mode is invoked by adc idle, the adc conversion completion w ill exit idle. power-down mode the power-down mode places the T89C51CC02 in a very low power state. power-down mode stops the oscillator, freezes all clock at known states. the cpu status prior to entering power-down mode is preserved, i.e., the program counter, program status word register retain their data for the duration of power-down mode. in addition, the sfrs and ram contents are preserved. the status of the port pins during power-down mode is detailed in table 13. entering power-down mode to enter power-down mode, set pd bit in pcon register. the T89C51CC02 enters the power-down mode upon execution of the instruction that sets pd bit. the instruction that sets pd bit is the last instruction executed.
23 T89C51CC02 4126f?can?12/03 exiting power-down mode note: if v dd was reduced during the power-down mode, do not exit power-down mode until v dd is restored to the normal operating level. there are two ways to exit the power-down mode: 1. generate an enabled external interrupt. ? the T89C51CC02 provides capability to exit from power-down using int0#, int1#. hardware clears pd bit in pcon register which starts the oscillator and restores the clocks to the cpu and peripherals. using intx# input, execution resumes when the input is released (see figure 8). execution resumes with the interrupt service routine. upon completion of the interrupt service routine, program execution resumes with the instruction immediately following the instruction that activated power-down mode. notes: 1. the external interrupt used to exit power-down mode must be configured as level sensitive (int0# and int1#) and must be assigned the highest priority. in addition, the duration of the interrupt must be long enough to allow the oscillator to stabilize. the execution will only resume when the interrupt is deasserted. 2. exit from power-down by external interrupt does not affect the sfrs nor the internal ram content. figure 8. power-down exit waveform using int1:0# 2. generate a reset. ? a logic high on the rst pin clears pd bit in pcon register directly and asynchronously. this starts the oscilla tor and restores the clock to the cpu and peripherals. program execution momentarily resumes with the instruction immediately following the instruction that activated power-down mode and may continue for a number of clock cycles before the internal reset algorithm takes control. reset initializes the T89C51CC02 and vectors the cpu to address 0000h. notes: 1. during the time that execution resumes, the internal ram cannot be accessed; how- ever, it is possible for the port pins to be accessed. to avoid unexpected outputs at the port pins, the instruction immediately following the instruction that activated the power-down mode should not write to a port pin or to the external ram. 2. exit from power-down by reset redefines all the sfrs, but does not affect the internal ram content. int1:0# osc power-down phase oscillator restart phase active phase active phase
24 T89C51CC02 4126f?can?12/03 registers table 15. pcon register pcon (s:87h) power control register reset value = 00x1 0000b not bit addressable 76543210 smod1 smod0 - pof gf1 gf0 pd idl bit number bit mnemonic description 7smod1 serial port mode bit 1 set to select double baud rate in mode 1, 2 or 3. 6smod0 serial port mode bit 0 clear to select sm0 bit in scon register. set to select fe bit in scon register. 5- reserved the value read from this bit is indeterminate. do not set this bit. 4pof power-off flag clear to recognize next reset type. set by hardware when v cc rises from 0 to its nominal voltage. can also be set by software. 3gf1 general purpose flag cleared by user for general purpose usage. set by user for general purpose usage. 2gf0 general purpose flag cleared by user for general purpose usage. set by user for general purpose usage. 1pd power-down mode bit cleared by hardware when reset occurs. set to enter power-down mode. 0idl idle mode bit clear by hardware when interrupt or reset occurs. set to enter idle mode.
25 T89C51CC02 4126f?can?12/03 data memory the T89C51CC02 provides data memory access in two different spaces: the internal space mapped in three separate segments: the lower 128 bytes ram segment. the upper 128 bytes ram segment. the expanded 256 bytes ram segment (xram). a fourth internal segment is available but dedicated to special function registers, sfrs, (addresses 80h to ffh) accessible by direct addressing mode. figure 9 shows the internal data memory spaces organization. figure 9. internal memory - ram internal space lower 128 bytes ram the lower 128 bytes of ram (see figure 10) are accessible from address 00h to 7fh using direct or indirect addressing modes. the lowest 32 bytes are grouped into 4 banks of 8 registers (r0 to r7). two bits rs0 and rs1 in psw register (see table 17) select which bank is in use according to table 16. this allows more efficient use of code space, since register instructions are shorter than instructions that use direct address- ing, and can be used for context switching in interrupt service routines. table 16. register bank selection the next 16 bytes above the register banks form a block of bit-addressable memory space. the c51 instruction set includes a wide selection of singlebit instructions, and the 128 bits in this area can be directly addressed by these instructions. the bit addresses in this area are 00h to 7fh. 256 bytes upper 128 bytes internal ram lower 128 bytes internal ram special function registers 80h 80h 00h ffh ffh 00h ffh direct addressing addressing 7fh internal xram direct or indirect indirect addressing rs1 rs0 description 0 0 register bank 0 from 00h to 07h 0 1 register bank 0 from 08h to 0fh 1 0 register bank 0 from 10h to 17h 1 1 register bank 0 from 18h to 1fh
26 T89C51CC02 4126f?can?12/03 figure 10. lower 128 bytes internal ram organization upper 128 bytes ram the upper 128 bytes of ram are accessible from address 80h to ffh using only indirect addressing mode. expanded ram the on-chip 256 bytes of expanded ram (xram) are accessible from address 0000h to 00ffh using indirect addressing mode through movx instructions. in this address range. note: lower 128 bytes ram, upper 128 bytes ram, and expanded ram are made of volatile memory cells. this means that the ram content is indeterminate after power-up and must then be initialized properly. bit-addressable space 4 banks of 8 registers r0-r7 30h 7fh (bit addresses 0-7fh) 20h 2fh 18h 1fh 10h 17h 08h 0fh 00h 07h
27 T89C51CC02 4126f?can?12/03 dual data pointer description the T89C51CC02 implements a second data pointer for speeding up code execution and reducing code size in case of intensive usage of external memory accesses. dptr0 and dptr1 are seen by the cpu as dptr and are accessed using the sfr addresses 83h and 84h that are the dph and dpl addresses. the dps bit in auxr1 register (see figure 18) is used to select whether dptr is the data pointer 0 or the data pointer 1 (see figure 11). figure 11. dual data pointer implementation application software can take advantage of the additional data pointers to both increase speed and reduce code size, for example, block operations (copy, compare?) are well served by using one data pointer as a ?source? pointer and the other one as a ?destination? pointer. hereafter is an example of block move implementation using the two pointers and coded in assembler. the latest c compiler takes also advantage of this feature by providing enhanced algorithm libraries. the inc instruction is a short (2 bytes) and fast (6 machine cycle) way to manipulate the dps bit in the auxr1 register. however, note that the inc instruction does not directly force the dps bit to a particular state, but simply toggles it. in simple routines, such as the block move example, only the fact that dps is toggled in the proper sequence mat- ters, not its actual value. in other words, the block move routine works the same whether dps is 0 or 1 on entry. ; ascii block move using dual data pointers ; modifies dptr0, dptr1, a and psw ; ends when encountering null character ; note: dps exits opposite to the entry state unless an extra inc auxr1 is added auxr1equ0a2h move:movdptr,#source ; address of source incauxr1 ; switch data pointers movdptr,#dest ; address of dest mv_loop:incauxr1; switch data pointers movxa,@dptr; get a byte from source incdptr; increment source address incauxr1; switch data pointers movx@dptr,a; write the byte to dest incdptr; increment dest address jnzmv_loop; check for null terminator end_move: 0 1 dph0 dph1 dpl0 0 1 dps auxr1.0 dph dpl dpl1 dptr dptr0 dptr1
28 T89C51CC02 4126f?can?12/03 registers table 17. psw register psw (s:d0h) program status word register reset value = 0000 0000b 76543210 cy ac f0 rs1 rs0 ov f1 p bit number bit mnemonic description 7cy carry flag carry out from bit 1 of alu operands. 6ac auxiliary carry flag carry out from bit 1 of addition operands. 5f0 user definable flag 0 4 - 3 rs1:0 register bank select bits refer to table 16 for bits description. 2ov overflow flag overflow set by arithmetic operations. 1f1 user definable flag 1 0p parity bit set when acc contains an odd number of 1?s. cleared when acc contains an even number of 1?s.
29 T89C51CC02 4126f?can?12/03 table 18. auxr1 register auxr1 (s:a2h) auxiliary control register 1 reset value = xxxx 00x0b note: 1. enboot is initialized with the invert bljb at reset. see in-system programming section. 76543210 - - enboot - gf3 0 - dps bit number bit mnemonic description 7 - 6 - reserved the value read from these bits is indeterminate. do not set these bits. 5enboot (1) enable boot flash set this bit to map the boot flash between f800h -ffffh clear this bit to disable boot flash. 4- reserved the value read from this bit is indeterminate. do not set this bit. 3gf3 general purpose flag 3 20 always zero this bit is stuck to logic 0 to allow inc auxr1 instruction without affecting gf3 flag. 1- reserved for data pointer extension 0dps data pointer select bit set to select second dual data pointer: dptr1. clear to select first dual data pointer: dptr0.
30 T89C51CC02 4126f?can?12/03 eeprom data memory the 2k bytes on-chip eeprom memory block is located at addresses 0000h to 07ffh of the xram/xram memory space and is selected by setting control bits in the eecon register. a read in the eeprom memory is done with a movx instruction. a physical write in the eeprom memory is done in two steps: write data in the column latches and transfer of all data latches into an eeprom memory row (programming). the number of data written on the page may vary from 1 up to 128 bytes (the page size). when programming, only the data written in the column latch is programmed and a ninth bit is used to obtain this feature. this provides the capability to program the whole memory by bytes, by page or by a number of bytes in a page. indeed, each ninth bit is set when the writing the corresponding byte in a row and all these ninth bits are reset after the writing of the complete eeprom row. write data in the column latches data is written by byte to the column latches as for an external ram memory. out of the 11 address bits of the data pointer, the 4 msbs are used for page selection (row) and 7 are used for byte selection. between two eeprom programming sessions, all the addresses in the column latches must stay on the same page, meaning that the 4 msb must no be changed. the following procedure is used to write to the column latches: save and disable interrupt set bit eee of eecon register load dptr with the address to write store a register with the data to be written execute a movx @dptr, a if needed loop the three last instructions until the end of a 128 bytes page restore interrupt note: the last page address used when loading the column latch is the one used to select the page programming address. programming the eeprom programming consists of the following actions: write one or more bytes of one page in the column latches. normally, all bytes must belong to the same page; if not, the last page address will be latched and the others discarded. launch programming by writing the control sequence (50h followed by a0h) to the eecon register. eebusy flag in eecon is then set by hardware to indicate that programming is in progress and that the eeprom segment is not available for reading. the end of programming is indicated by a hardware clear of the eebusy flag. note: the sequence 5xh and axh must be executed without instructions between then other- wise the programming is aborted. read data the following procedure is used to read the data stored in the eeprom memory: save and disable interrupt set bit eee of eecon register load dptr with the address to read execute a movx a, @dptr restore interrupt
31 T89C51CC02 4126f?can?12/03 examples ;*f************************************************************************* ;* name: api_rd_eeprom_byte ;* dptr contain address to read. ;* acc contain the reading value ;* note: before execute this function, be sure the eeprom is not busy ;*************************************************************************** api_rd_eeprom_byte: ; save and clear ea mov eecon, #02h; map eeprom in xram space movx a, @dptr mov eecon, #00h; unmap eeprom ; restore ea ret ;*f************************************************************************* ;* name: api_ld_eeprom_cl ;* dptr contain address to load ;* acc contain value to load ;* note: in this example we load only 1 byte, but it is possible upto ;* 128 bytes. ;* before execute this function, be sure the eeprom is not busy ;*************************************************************************** api_ld_eeprom_cl: ; save and clear ea mov eecon, #02h ; map eeprom in xram space movx @dptr, a moveecon, #00h; unmap eeprom ; restore ea ret ;*f************************************************************************* ;* name: api_wr_eeprom ;* note: before execute this function, be sure the eeprom is not busy ;*************************************************************************** api_wr_eeprom: ; save and clear ea mov eecon, #050h mov eecon, #0a0h ; restore ea ret
32 T89C51CC02 4126f?can?12/03 registers table 19. eecon register eecon (s:0d2h) eeprom control register reset value = xxxx xx00b not bit addressable 76543210 eepl3 eepl2 eepl1 eepl0 - - eee eebusy bit number bit mnemonic description 7 - 4 eepl3-0 programming launch command bits write 5xh followed by axh to eepl to launch the programming. 3- reserved the value read from this bit is indeterminate. do not set this bit. 2- reserved the value read from this bit is indeterminate. do not set this bit. 1 eee enable eeprom space bit set to map the eeprom space during movx instructions (write in the column latches) clear to map the xram space during movx. 0 eebusy programming busy flag set by hardware when programming is in progress. cleared by hardware when programming is done. can not be set or cleared by software.
33 T89C51CC02 4126f?can?12/03 program/code memory the T89C51CC02 implement 16k bytes of on-chip program/code memory. the flash memory increases eprom and rom functionality by in-circuit electrical era- sure and programming. thanks to the internal charge pump, the high voltage needed for programming or erasing flash cells is generated on-chip using the standard v dd volt- age. thus, the flash memory can be programmed using only one voltage and allows in- system programming (isp). hardware programming mode is also available using spe- cific programming tool. figure 12. program/code memory organization flash memory architecture T89C51CC02 features two on-chip flash memories: flash memory fm0: containing 16k bytes of program memory (user space) organized into 128 bytes pages, flash memory fm1: 2k bytes for boot loader and application programming interfaces (api). the fm0 can be program by both parallel programming and serial isp whereas fm1 supports only parallel programming by programmers. the isp mode is detailed in the ?in-system programming? section. all read/write access operations on flash memory by user application are managed by a set of api described in the ?in-system programming? section. figure 13. flash memory architecture 0000h 16k bytes 3fffh internal flash 3fffh 16k bytes flash memory fm0 0000h hardware security (1 byte) column latches (128 bytes) user space extra row (128 bytes) 2k bytes flash memory fm1 boot space ffffh f800h fm1 mapped between f800h and ffffh when bit enboot is set in auxr1 register
34 T89C51CC02 4126f?can?12/03 fm0 memory architecture the flash memory is made up of 4 blocks (see figure 13): 1. the memory array (user space) 16k bytes 2. the extra row 3. the hardware security bits 4. the column latch registers user space this space is composed of a 16k bytes flash memory organized in 128 pages of 128 bytes. it contains the user?s application code. extra row (xrow) this row is a part of fm0 and has a size of 128 bytes. the extra row may contain infor- mation for boot loader usage. hardware security byte the hardware security byte space is a part of fm0 and has a size of 1 byte. the 4 msb can be read/written by software, the 4 lsb can only be read by software and written by hardware in parallel mode. column latches the column latches, also part of fm0, have a size of full page (128 bytes). the column latches are the entrance buffers of the three previous memory locations (user array, xrow and hardware security byte). cross flash memory access description the fm0 memory can be programmed as describe on table 20. programming fm0 from fm0 is impossible. the fm1 memory can be program only by parallel programming. table 20 show all software flash access allowed. table 20. cross flash memory access code executing from action fm0 (user flash) fm1 (boot flash) fm0 (user flash) read ok - load column latch ok - write - - fm1 (boot flash) read ok ok load column latch ok - write ok -
35 T89C51CC02 4126f?can?12/03 overview of fm0 operations the cpu interfaces the flash memory through the fcon register and auxr1 register. these registers are used to: map the memory spaces in the adressable space launch the programming of the memory spaces get the status of the flash memory (busy/not busy) mapping of the memory space by default, the user space is accessed by movc instruction for read only. the column latches space is made accessible by setting the fps bit in fcon register. writing is possible from 0000h to 3fffh, address bits 6 to 0 are used to select an address within a page while bits 14 to 7 are used to select the programming address of the page. setting fps bit takes precedence on the eee bit in eecon register. the other memory spaces (user, extra row, hardware security) are made accessible in the code segment by programming bits fmod0 and fmod1 in fcon register in accor- dance with table 21. a movc instruction is then used for reading these spaces. table 21. fm0 blocks select bits launching programming fpl3:0 bits in fcon register are used to secure the launch of programming. a specific sequence must be written in these bits to unlock the write protection and to launch the programming. this sequence is 5xh followed by axh. table 22 summarizes the memory spaces to program according to fmod1:0 bits. table 22. programming spaces note: the sequence 5xh and axh must be executing without instructions between them other- wise the programming is aborted. interrupts that may occur during programming time must be disabled to avoid any spuri- ous exit of the programming mode. fmod1 fmod0 fm0 adressable space 0 0 user (0000h-3fffh) 0 1 extra row(ff80h-ffffh) 1 0 hardware security byte (0000h) 11reserved write to fcon operation fpl3:0 fps fmod1 fmod0 user 5 x 0 0 no action ax00 write the column latches in user space extra row 5 x 0 1 no action ax01 write the column latches in extra row space hardware security byte 5 x 1 0 no action a x 1 0 write the fuse bits space reserved 5 x 1 1 no action a x 1 1 no action
36 T89C51CC02 4126f?can?12/03 status of the flash memory the bit fbusy in fcon register is used to indicate the status of programming. fbusy is set when programming is in progress. selecting fm1 the bit enboot in auxr1 register is used to map fm1 from f800h to ffffh. loading the column latches any number of data from 1 byte to 128 bytes can be loaded in the column latches. this provides the capability to program the whole memory by byte, by page or by any number of bytes in a page. when programming is launched, an automatic erase of the locations loaded in the col- umn latches is first performed, then programming is effectively done. thus no page or block erase is needed and only the loaded data are programmed in the corresponding page. the following procedure is used to load the column latches and is summarized in figure 14: save then disable interrupt and map the column latch space by setting fps bit. load the dptr with the address to load. load accumulator register with the data to load. execute the movx @dptr, a instruction. if needed loop the three last instructions until the page is completely loaded. unmap the column latch and restore interrupt
37 T89C51CC02 4126f?can?12/03 figure 14. column latches loading procedure (1) note: 1. the last page address used when loading the column latch is the one used to select the page programming address. programming the flash spaces user the following procedure is used to program the user space and is summarized in figure 15: load up to one page of data in the column latches from address 0000h to 3fffh. save then disable the interrupts. launch the programming by writing the data sequence 50h followed by a0h in fcon register.this step must be executed from fm1. the end of the programming indicated by the fbusy flag cleared. restore the interrupts. extra row the following procedure is used to program the extra row space and is summarized in figure 15: load data in the column latches from address ff80h to ffffh. save then disable the interrupts. launch the programming by writing the data sequence 52h followed by a2h in fcon register. this step of the procedure must be executed from fm1. the end of the programming indicated by the fbusy flag cleared. restore the interrupts. column latches loading data load dptr = address acc = data exec: movx @dptr, a last byte to load? column latches mapping fcon = 08h (fps = 1) data memory mapping fcon = 00h (fps = 0) save & disable it ea = 0 restore it
38 T89C51CC02 4126f?can?12/03 figure 15. flash and extra row programming procedure hardware security byte the following procedure is used to program the hardware security byte space and is summarized in figure 16: set fps and map hardware byte (fcon = 0x0c) save then disable the interrupts. load dptr at address 0000h. load accumulator register with the data to load. execute the movx @dptr, a instruction. launch the programming by writing the data sequence 54h followed by a4h in fcon register. this step of the procedure must be executed from fm1. the end of the programming indicated by the fbusy flag cleared. restore the interrupts flash spaces programming save & disable it ea = 0 launch programming fcon = 5xh fcon = axh end programming restore it column latches loading see figure 14 fbusy cleared? clear mode fcon = 00h
39 T89C51CC02 4126f?can?12/03 figure 16. hardware programming procedure reading the flash spaces user the following procedure is used to read the user space: read one byte in accumulator by executing movc a,@a+dptr with a+dptr is the address of the code byte to read. note: fcon must be cleared (00h) when not used. extra row the following procedure is used to read the extra row space and is summarized in figure 17: map the extra row space by writing 02h in fcon register. read one byte in accumulator by executing movc a,@a+dptr with a= 0 & dptr= ff80h to ffffh. clear fcon to unmap the extra row. hardware security byte the following procedure is used to read the hardware security byte and is sum- marized in figure 17: map the hardware security space by writing 04h in fcon register. read the byte in accumulator by executing movc a,@a+dptr with a= 0 & dptr= 0000h. clear fcon to unmap the hardware security byte. flash spaces programming save & disable it ea = 0 launch programming fcon = 54h fcon = a4h end programming restoreit fbusy cleared? clear mode fcon = 00h data load dptr = 00h acc = data exec: movx @dptr, a fcon = 0ch save & disable it ea = 0 end loading restore it
40 T89C51CC02 4126f?can?12/03 figure 17. reading procedure note: aa = 10 for the hardware security byte. flash protection from parallel programming the three lock bits in hardware security byte (see ?in-system programming? section) are programmed according to table 23 provide different level of protection for the on- chip code and data located in fm0 and fm1. the only way to write this bits are the parallel mode. they are set by default to level 3. table 23. program lock bit note: 1. program lock bits u: unprogrammed p: programmed warning: security level 2 and 3 should only be programmed after flash and core verification. preventing flash corruption see section ?power management?. flash spaces reading flash spaces mapping fcon = 00000aa0b data read dptr = address acc= 0 exec: movc a, @a+dptr clear mode fcon = 00h program lock bits protection description security level lb0 lb1 lb2 1uuu no program lock features enabled. movc instruction executed from external program memory returns code data. 2 p u u parallel programming of the flash is disabled. 3upu same as 2, also verify through parallel programming interface is disabled. this is the factory defaul programming.
41 T89C51CC02 4126f?can?12/03 registers table 24. fcon register fcon register fcon (s:d1h) flash control register reset value = 0000 0000b 76543210 fpl3 fpl2 fpl1 fpl0 fps fmod1 fmod0 fbusy bit number bit mnemonic description 7 - 4 fpl3:0 programming launch command bits write 5xh followed by axh to launch the programming according to fmod1:0. (see table 22.) 3fps flash map program space set to map the column latch space in the data memory space. clear to re-map the data memory space. 2 - 1 fmod1:0 flash mode see table 21 or table 22. 0 fbusy flash busy set by hardware when programming is in progress. clear by hardware when programming is done. can not be changed by software.
42 T89C51CC02 4126f?can?12/03 operation cross memory access space addressable in read and write are: ram eram (expanded ram access by movx) eeprom data fm0 ( user flash ) hardware byte xrow boot flash flash column latch the table below provides the different kind of memory which can be accessed from dif- ferent code location. table 25. cross memory access action ram eram boot flash fm0 e2 data hardware byte xrow boot flash read ok ok ok ok - write - ok (rww) ok (rww) ok (rww) ok (rww) fm0 read ok (confidential) ok ok -ok - write - ok (idle) ok(rww) - -ok
43 T89C51CC02 4126f?can?12/03 sharing instructions table 26. instructions shared note: by cl : using column latch table 27. read movx a, @dptr table 28. write movx @dptr,a action ram eram eeprom data boot flash fm0 hardware byte xrow read mov movx movx movc movc movc movc write mov movx movx - by cl by cl by cl eee bit in eecon register fps in fcon register enboot eram eeprom data flash column latch 00xwinner 01xwinner 10x winner 11xwinner eee bit in eecon register fps bit in fcon register enboot eram eeprom data flash column latch 00xwinner 01x winner 1 0 x winner 11x winner
44 T89C51CC02 4126f?can?12/03 table 29. read movc a, @dptr code execution fcon register enboot dptr fm1 fm0 xrow hardware byte fmod1 fmod0 fps from fm0 00x 0 0000h to 3fffh winner 1 0000h to 3fffh winner f800h to ffffh do not use this configuration 01x x 0000 to 007fh see (1) winner 10x x x winner 11x 0 000h to 3fffh winner 1 0000h to 3fffh winner f800h to ffffh do not use this configuration from fm1 (enboot =1 00 0 1 0000h to 3fff winner f800h to ffffh winner 0x na 1 1 x winner 0x na 01x 1 0000h to 007h see (2) winner 0na 10x 1 x winner 0na 11x 1 000h to 3fffh winner 0na 1. for dptr higher than 007fh only lowest 7 bits are decoded, thus the behavior is the same as for addresses from 0000h to 007fh 2. for dptr higher than 007fh only lowest 7 bits are decoded, thus the behavior is the same as for addresses from 0000h to 007fh
45 T89C51CC02 4126f?can?12/03 in-system programming (isp) with the implementation of the user space (fm0) and the boot space (fm1) in flash technology the T89C51CC02 allows the system engineer the development of applica- tions with a very high level of flexibility. this flexibility is based on the possibility to alter the customer program at any stages of a product?s life: before mounting the chip on the pcb, fm0 flash can be programmed with the application code. fm1 is always preprogrammed by atmel with a bootloader (chip can be ordered with can bootloader or uart bootloader). (1) once the chip is mounted on the pcb, it can be programmed by serial mode via the can bus or uart. note: 1. the user can also program his own bootloader in fm1. this isp allows code modification over the total lifetime of the product. besides the default bootloaders atmel provide customers all the needed application- programming-interfaces (api) which are needed for the isp. the api are located in the boot memory. this allow the customer to have a full use of the 16-kbyte user memory. flash programming and erasure there are three methods for programming the flash memory: the atmel bootloader located in fm1 is activated by the application. low level api routines (located in fm1)will be used to program fm0. the interface used for serial downloading to fm0 is the uart or the can. api can be called also by user?s bootloader located in fm0 at [sbv]00h. a further method exist in activating the atmel boot loader by hardware activation. see the section ?hardware security byte?. the fm0 can be programmed also by the parallel mode using a programmer. figure 18. flash memory mapping f800h 3fffh 16k bytes flash memory 2k bytes iap bootloader fm0 fm1 custom bootloader [sbv]00h ffffh fm1 mapped between f800h and ffff h when api called 0000h
46 T89C51CC02 4126f?can?12/03 boot process software boot process example many algorithms can be used for the software boot process. below are descriptions of the different flags and bytes. boot loader jump bit (bljb): - this bit indicates if on reset the user wants to jump to this application at address @0000h on fm0 or execute the boot loader at address @f800h on fm1. - bljb = 0 (i.e. bootloader fm1 executed after a reset) is the default atmel factory pro- gramming. -to read or modify this bit, the apis are used. boot vector address (sbv): - this byte contains the msb of the user boot loader address in fm0. - the default value of sbv is ffh (no user boot loader in fm0). - to read or modify this byte, the apis are used. extra byte (eb) & boot status byte (bsb): - these bytes are reserved for customer use. - to read or modify these bytes, the apis are used. figure 19. hardware boot process algorithm application- programming-interface several application program interface (api) calls are available for use by an application program to permit selective erasing and programming of flash pages. all calls are made by functions. all these apis are described in detail in the following documents on the atmel web site. ? datasheet bootloader can T89C51CC02. ? datasheet bootloader uart T89C51CC02. reset bljb == 0 ? hardware software bootloader in fm1 application in fm0 bit enboot in auxr1 register is initialized with bljb inverted. enboot = 0 pc = 0000h enboot = 1 pc = f800h example, if bljb=0, enboot is set (=1) during reset, thus the bootloader is executed after the reset.
47 T89C51CC02 4126f?can?12/03 xrow bytes the extra row (xrow) includes 128 bytes. some of these bytes are used for spe- cific purpose in conjonction with the bootloader. table 30. xrow mapping hardware conditions it is possible to force the controller to execute the bootloader after a reset with hard- ware conditions. during the first programming, the user can define a configuration on port1 that will be recognized by the chip as the hardware conditions during a reset. if this condition is met, the chip will start executing the bootloader at the end of the reset. see a detailed description in the applicable document. ? datasheet bootloader can T89C51CC02. ? datasheet bootloader uart T89C51CC02. description default value address copy of the manufacturer code 58h 30h copy of the device id#1: family code d7h 31h copy of the device id#2: memories size and type bbh 60h copy of the device id#3: name and revision ffh 61h
48 T89C51CC02 4126f?can?12/03 hardware security byte table 31. hardware security byte default value after erasing chip: ffh notes: 1. only the 4 msb bits can be accessed by software. 2. the 4 lsb bits can only be accessed by parallel mode. 76543210 x2b bljb - - - lb2 lb1 lb0 bit number bit mnemonic description 7x2b x2 bit set this bit to start in standard mode clear this bit to start in x2 mode. 6bljb boot loader jump bit - 1: to start the user?s application on next reset (@0000h) located in fm0, - 0: to start the boot loader(@f800h) located in fm1. 5 - 3 - reserved the value read from these bits are indeterminate. 2 - 0 lb2:0 lock bits (see table 22)
49 T89C51CC02 4126f?can?12/03 serial i/o port the T89C51CC02 i/o serial port is compatible with the i/o serial port in the 80c52. it provides both synchronous and asynchronous communication modes. it operates as a universal asynchronous receiver and transmitter (uart) in three full-duplex modes (modes 1, 2 and 3). asynchronous transmission and reception can occur simultaneously and at different baud rates serial i/o port includes the following enhancements: framing error detection automatic address recognition figure 20. serial i/o port block diagram framing error detection framing bit error detection is provided for the three asynchronous modes. to enable the framing bit error detection feature, set smod0 bit in pcon register. figure 21. framing error block diagram when this feature is enabled, the receiver checks each incoming data frame for a valid stop bit. an invalid stop bit may result from noise on the serial lines or from simultaneous transmission by two cpus. if a valid stop bit is not found, the framing error bit (fe) in scon register bit is set. the software may examine the fe bit after each reception to check for data errors. once set, only software or a reset clears the fe bit. subsequently received frames with valid stop bits cannot clear the fe bit. when the fe feature is enabled, ri rises on the stop bit instead of the last data bit (see figure 22 and figure 23). write sbuf ri ti sbuf transmitter sbuf receiver ib bus mode 0 transmit receive shift register load sbuf read sbuf scon reg interrupt request serial port txd rxd ri ti rb8 tb8 ren sm2 sm1 sm0/fe idl pd gf0 gf1 pof - smod0 smod1 to uart framing error control sm0 to uart mode control set fe bit if stop bit is 0 (framing error)
50 T89C51CC02 4126f?can?12/03 figure 22. uart timing in mode 1 figure 23. uart timing in modes 2 and 3 automatic address recognition the automatic address recognition feature is enabled when the multiprocessor commu- nication feature is enabled (sm2 bit in scon register is set). implemented in the hardware, automatic address recognition enhances the multiproces- sor communication feature by allowing the serial port to examine the address of each incoming command frame. only when the serial port recognizes its own address will the receiver set the ri bit in the scon register to generate an interrupt. this ensures that the cpu is not interrupted by command frames addressed to other devices. if necessary, the user can enable the automatic address recognition feature in mode 1. in this configuration, the stop bit takes the place of the ninth data bit. bit ri is set only when the received command frame address matches the device?s address and is termi- nated by a valid stop bit. to support automatic address recognition, a device is identified by a given address and a broadcast address. note: the multiprocessor communication and automatic address recognition features cannot be enabled in mode 0 (i.e. setting sm2 bit in scon register in mode 0 has no effect). given address each device has an individual address that is specified in the saddr register; the saden register is a mask byte that contains don?t-care bits (defined by zeros) to form the device?s given address. the don?t-care bits provide the flexibility to address one or more slaves at a time. the following example illustrates how a given address is formed. to address a device by its individual address, the saden mask byte must be 1111 1111b . for example: saddr0101 0110b saden 1111 1100b given0101 01xxb data byte ri smod0 = x stop bit start bit rxd d7 d6 d5 d4 d3 d2 d1 d0 fe smod0 = 1 ri smod0 = 0 data byte ninth bit stop bit start bit rxd d8 d7 d6 d5 d4 d3 d2 d1 d0 ri smod0 = 1 fe smod0 = 1
51 T89C51CC02 4126f?can?12/03 here is an example of how to use given addresses to address different slaves: slave a:saddr1111 0001b saden 1111 1010b given1111 0x0xb slave b:saddr1111 0011b saden 1111 1001b given1111 0xx1b slave c:saddr1111 0011b saden 1111 1101b given1111 00x1b the saden byte is selected so that each slave may be addressed separately. for slave a, bit 0 (the lsb) is a don?t-care bit; for slaves b and c, bit 0 is a 1. to com- municate with slave a only, the master must send an address where bit 0 is clear (e.g. 1111 0000b ). for slave a, bit 1 is a 0; for slaves b and c, bit 1 is a don?t care bit. to communicate with slaves a and b, but not slave c, the master must send an address with bits 0 and 1 both set (e.g. 1111 0011b ). to communicate with slaves a, b and c, the master must send an address with bit 0 set, bit 1 clear, and bit 2 clear (e.g. 1111 0001b ). broadcast address a broadcast address is formed from the logical or of the saddr and saden registers with zeros defined as don?t-care bits, e.g.: saddr 0101 0110b saden 1111 1100b saddr or saden1111 111xb the use of don?t-care bits provides flexib ility in defining the br oadcast address, however in most applications, a broadcast address is ffh. the following is an example of using broadcast addresses: slave a:saddr1111 0001b saden 1111 1010b given1111 1x11b, slave b:saddr1111 0011b saden 1111 1001b given1111 1x11b, slave c:saddr=1111 0010b saden 1111 1101b given1111 1111b for slaves a and b, bit 2 is a don?t care bit; for slave c, bit 2 is set. to communicate with all of the slaves, the master must send an address ffh. to communicate with slaves a and b, but not slave c, the master can send and address fbh.
52 T89C51CC02 4126f?can?12/03 registers table 32. scon register scon (s:98h) serial control register reset value = 0000 0000b bit addressable 76543210 fe/sm0 sm1 sm2 ren tb8 rb8 ti ri bit number bit mnemonic description 7 fe framing error bit (smod0 = 1 ) clear to reset the error state, not cleared by a valid stop bit. set by hardware when an invalid stop bit is detected. sm0 serial port mode bit 0 (smod0 = 0) refer to sm1 for serial port mode selection. 6sm1 serial port mode bit 1 sm0 sm1 mode baud rate 0 0 shift register f xtal /12 (or f xtal /6 in mode x2) 0 1 8-bit uart variable 1 0 9bit uart f xtal /64 or f xtal /32 1 1 9bit uart variable 5sm2 serial port mode 2 bit/multiprocessor communication enable bit clear to disable multiprocessor communication feature. set to enable multiprocessor communication feature in mode 2 and 3. 4ren reception enable bit clear to disable serial reception. set to enable serial reception. 3tb8 transmitter bit 8/ninth bit to transmit in modes 2 and 3 clear to transmit a logic 0 in the 9th bit. set to transmit a logic 1 in the 9th bit. 2rb8 receiver bit 8/ninth bit received in modes 2 and 3 cleared by hardware if 9th bit received is a logic 0. set by hardware if 9th bit received is a logic 1. 1ti transmit interrupt flag clear to acknowledge interrupt. set by hardware at the end of the 8th bit time in mode 0 or at the beginning of the stop bit in the other modes. 0ri receive interrupt flag clear to acknowledge interrupt. set by hardware at the end of the 8th bit time in mode 0, see figure 22. and figure 23. in the other modes.
53 T89C51CC02 4126f?can?12/03 table 33. saden register saden (s:b9h) slave address mask register reset value = 0000 0000b not bit addressable table 34. saddr register saddr (s:a9h) slave address register reset value = 0000 0000b not bit addressable table 35. sbuf register sbuf (s:99h) serial data buffer reset value = 0000 0000b not bit addressable 76543210 bit number bit mnemonic description 7 - 0 mask data for slave individual address 76543210 bit number bit mnemonic description 7 - 0 slave individual address 76543210 bit number bit mnemonic description 7 - 0 data sent/received by serial i/o port
54 T89C51CC02 4126f?can?12/03 table 36. pcon register pcon (s:87h) power control register reset value = 00x1 0000b not bit addressable 76543210 smod1 smod0 - pof gf1 gf0 pd idl bit number bit mnemonic description 7smod1 serial port mode bit 1 set to select double baud rate in mode 1, 2 or 3. 6smod0 serial port mode bit 0 clear to select sm0 bit in scon register. set to select fe bit in scon register. 5- reserved the value read from this bit is indeterminate. do not set this bit. 4pof power-off flag clear to recognize next reset type. set by hardware when v cc rises from 0 to its nominal voltage. can also be set by software. 3gf1 general purpose flag cleared by user for general purpose usage. set by user for general purpose usage. 2gf0 general purpose flag cleared by user for general purpose usage. set by user for general purpose usage. 1pd power-down mode bit cleared by hardware when reset occurs. set to enter power-down mode. 0idl idle mode bit clear by hardware when interrupt or reset occurs. set to enter idle mode.
55 T89C51CC02 4126f?can?12/03 timers/counters the T89C51CC02 implements two general-purpose, 16-bit timers/counters. such are identified as timer 0 and timer 1, and can be independently configured to operate in a variety of modes as a timer or an event counter. when operating as a timer, the timer/counter runs for a programmed length of time, then issues an interrupt request. when operating as a counter, the timer/counter counts negative transitions on an external pin. after a preset number of counts, the counter issues an interrupt request. the various operating modes of each timer/counter are described in the following sections. timer/counter operations a basic operation is timer registers thx and tlx (x = 0, 1) connected in cascade to form a 16-bit timer. setting the run control bit (trx) in tcon register (see figure 37) turns the timer on by allowing the selected input to increment tlx. when tlx overflows it increments thx; when thx overflows it sets the timer overflow flag (tfx) in tcon register. setting the trx does not clear the thx and tlx timer registers. timer regis- ters can be accessed to obtain the current count or to enter preset values. they can be read at any time but trx bit must be cleared to preset their values, otherwise the behav- ior of the timer/counter is unpredictable. the c/tx# control bit selects timer operation or counter operation by selecting the divided-down peripheral clock or external pin tx as the source for the counted signal. trx bit must be cleared when changing the mode of operation, otherwise the behavior of the timer/counter is unpredictable. for timer operation (c/tx# = 0), the timer register counts the divided-down peripheral clock. the timer register is incremented once every peripheral cycle (6 peripheral clock periods). the timer clock rate is f per /6, i.e. f osc /12 in standard mode or f osc /6 in x2 mode. for counter operation (c/tx# = 1), the time r register counts the negative transitions on the tx external input pin. the external input is sampled every peripheral cycles. when the sample is high in one cycle and low in the next one, the counter is incremented. since it takes 2 cycles (12 peripheral clock periods) to recognize a negative transition, the maximum count rate is f per /12, i.e. f osc /24 in standard mode or f osc /12 in x2 mode. there are no restrictions on the duty cycle of the external input signal, but to ensure that a given level is sampled at least once before it changes, it should be held for at least one full peripheral cycle. timer 0 timer 0 functions as either a timer or event counter in four modes of operation. figure 24 through figure 27 show the logical configuration of each mode. timer 0 is controlled by the four lower bits of tmod register (see figure 38) and bits 0, 1, 4 and 5 of tcon register (see figure 37). tmod register selects the method of timer gating (gate0), timer or counter operation (t/c0#) and mode of operation (m10 and m00). tcon register provides timer 0 control functions: overflow flag (tf0), run control bit (tr0), interrupt flag (ie0) and interrupt type control bit (it0). for normal timer operation (gate0 = 0), setting tr0 allows tl0 to be incremented by the selected input. setting gate0 and tr0 allows external pin int0# to control timer operation. timer 0 overflow (count rolls over from all 1s to all 0s) sets tf0 flag generating an inter- rupt request. it is important to stop timer/counter before changing mode.
56 T89C51CC02 4126f?can?12/03 mode 0 (13-bit timer) mode 0 configures timer 0 as an 13-bit timer which is set up as an 8-bit timer (th0 register) with a modulo 32 prescaler implemented with the lower five bits of tl0 register (see figure 24). the upper three bits of tl0 register are indeterminate and should be ignored. prescaler overflow increments th0 register. figure 24. timer/counter x (x= 0 or 1) in mode 0 mode 1 (16-bit timer) mode 1 configures timer 0 as a 16-bit timer with th0 and tl0 registers connected in cascade (see figure 25). the selected input increments tl0 register. figure 25. timer/counter x (x= 0 or 1) in mode 1 mode 2 (8-bit timer with auto- reload) mode 2 configures timer 0 as an 8-bit timer (tl0 register) that automatically reloads from th0 register (see figure 26). tl0 overflow sets tf0 flag in tcon register and reloads tl0 with the contents of th0, which is preset by software. when the interrupt request is serviced, hardware clears tf0. the reload leaves th0 unchanged. the next reload value may be changed at any time by writing it to th0 register. ftx clock trx tcon reg tfx tcon reg 0 1 gatex tmod reg 6 overflow timer x interrupt request c/tx# tmod reg tlx (5 bits) thx (8 bits) intx# tx see section ?clock? trx tcon reg tfx tcon reg 0 1 gatex tmod reg overflow timer x interrupt request c/tx# tmod reg tlx (8 bits) thx (8 bits) intx# tx ftx clock 6 see section ?clock?
57 T89C51CC02 4126f?can?12/03 figure 26. timer/counter x (x= 0 or 1) in mode 2 mode 3 (two 8-bit timers) mode 3 configures timer 0 such that registers tl0 and th0 operate as separate 8-bit timers (see figure 27). this mode is provided for applications requiring an additional 8- bit timer or counter. tl0 uses the timer 0 control bits c/t0# and gate0 in tmod reg- ister, and tr0 and tf0 in tcon register in the normal manner. th0 is locked into a timer function (counting f per /6) and takes over use of the timer 1 interrupt (tf1) and run control (tr1) bits. thus, operation of timer 1 is restricted when timer 0 is in mode 3. figure 27. timer/counter 0 in mode 3: two 8-bit counters timer 1 timer 1 is identical to timer 0 excepted for mode 3 which is a hold-count mode. follow- ing comments help to understand the differences: timer 1 functions as either a timer or event counter in three modes of operation. figure 24 to figure 26 show the logical configuration for modes 0, 1, and 2. timer 1?s mode 3 is a hold-count mode. timer 1 is controlled by the four high-order bits of tmod register (see figure 38) and bits 2, 3, 6 and 7 of tcon register (see figure 37). tmod register selects the method of timer gating (gate1), timer or counter operation (c/t1#) and mode of operation (m11 and m01). tcon register provides timer 1 control functions: overflow flag (tf1), run control bit (tr1), interrupt flag (ie1) and interrupt type control bit (it1). timer 1 can serve as the baud rate generator for the serial port. mode 2 is best suited for this purpose. trx tcon reg tfx tcon reg 0 1 gatex tmod reg overflow timer x interrup t reques t c/tx# tmod reg tlx (8 bits) thx (8 bits) intx# tx ftx clock 6 see section ?clock? tr0 tcon.4 tf0 tcon.5 int0# 0 1 gate0 tmod.3 overflow timer 0 interrup t reques t c/t0# tmod.2 tl0 (8 bits) tr1 tcon.6 th0 (8 bits) tf1 tcon.7 overflow timer 1 interrup t reques t t0 ftx clock 6 ftx clock 6 see section ?clock?
58 T89C51CC02 4126f?can?12/03 for normal timer operation (gate1= 0), setting tr1 allows tl1 to be incremented by the selected input. setting gate1 and tr1 allows external pin int1# to control timer operation. timer 1 overflow (count rolls over from all 1s to all 0s) sets the tf1 flag generating an interrupt request. when timer 0 is in mode 3, it uses timer 1?s overflow flag (tf1) and run control bit (tr1). for this situation, use timer 1 only for applications that do not require an interrupt (such as a baud rate generator for the serial port) and switch timer 1 in and out of mode 3 to turn it off and on. it is important to stop timer/counter before changing mode. mode 0 (13-bit timer) mode 0 configures timer 1 as a 13-bit timer, which is set up as an 8-bit timer (th1 reg- ister) with a modulo-32 prescaler implemented with the lower 5 bits of the tl1 register (see figure 24). the upper 3 bits of tl1 regist er are ignored. prescaler overflow incre- ments th1 register. mode 1 (16-bit timer) mode 1 configures timer 1 as a 16-bit timer with th1 and tl1 registers connected in cascade (see figure 25). the selected input increments tl1 register. mode 2 (8-bit timer with auto- reload) mode 2 configures timer 1 as an 8-bit timer (tl1 register) with automatic reload from th1 register on overflow (see figure 26). tl1 overflow sets tf1 flag in tcon register and reloads tl1 with the contents of th1, which is preset by software. the reload leaves th1 unchanged. mode 3 (halt) placing timer 1 in mode 3 causes it to halt and hold its count. this can be used to halt timer 1 when tr1 run control bit is not available i.e. when timer 0 is in mode 3. interrupt each timer handles one interrupt source that is the timer overflow flag tf0 or tf1. this flag is set every time an overflow occurs. fl ags are cleared when vectoring to the timer interrupt routine. interrupts are enabled by setting etx bit in ien0 register. this assumes interrupts are globally enabled by setting ea bit in ien0 register. figure 28. timer interrupt system tf0 tcon.5 et0 ien0.1 timer 0 interrupt request tf1 tcon.7 et1 ien0.3 timer 1 interrupt request
59 T89C51CC02 4126f?can?12/03 registers table 37. tcon register tcon (s:88h) timer/counter control register reset value = 0000 0000b 76543210 tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 bit number bit mnemonic description 7tf1 timer 1 overflow flag cleared by hardware when processor vectors to interrupt routine. set by hardware on timer/counter overflow, when timer 1 register overflows. 6tr1 timer 1 run control bit clear to turn off timer/counter 1. set to turn on timer/counter 1. 5tf0 timer 0 overflow flag cleared by hardware when processor vectors to interrupt routine. set by hardware on timer/counter overflow, when timer 0 register overflows. 4tr0 timer 0 run control bit clear to turn off timer/counter 0. set to turn on timer/counter 0. 3ie1 interrupt 1 edge flag cleared by hardware when interrupt is processed if edge-triggered (see it1). set by hardware when external interrupt is detected on int1# pin. 2it1 interrupt 1 type control bit clear to select low level active (level triggered) for external interrupt 1 (int1#). set to select falling edge active (edge triggered) for external interrupt 1. 1ie0 interrupt 0 edge flag cleared by hardware when interrupt is processed if edge-triggered (see it0). set by hardware when external interrupt is detected on int0# pin. 0it0 interrupt 0 type control bit clear to select low level active (level triggered) for external interrupt 0 (int0#). set to select falling edge active (edge triggered) for external interrupt 0.
60 T89C51CC02 4126f?can?12/03 table 38. tmod register tmod (s:89h) timer/counter mode control register reset value = 0000 0000b notes: 1. reloaded from th1 at overflow. 2. reloaded from th0 at overflow. table 39. th0 register th0 (s:8ch) timer 0 high byte register reset value = 0000 0000b 76543210 gate1 c/t1# m11 m01 gate0 c/t0# m10 m00 bit number bit mnemonic description 7gate1 timer 1 gating control bit clear to enable timer 1 whenever tr1 bit is set. set to enable timer 1 only while int1# pin is high and tr1 bit is set. 6c/t1# timer 1 counter/timer select bit clear for timer operation: timer 1 counts the divided-down system clock. set for counter operation: timer 1 counts negative transitions on external pin t1. 5m11 timer 1 mode select bits m11 m01 operating mode 0 0 mode 0: 8-bit timer/counter (th1) with 5bit prescaler (tl1). 0 1 mode 1: 16-bit timer/counter. 1 1 mode 3: timer 1 halted. retains count. 1 0 mode 2: 8-bit auto-reload timer/counter (tl1). (1) 4m01 3gate0 timer 0 gating control bit clear to enable timer 0 whenever tr0 bit is set. set to enable timer/counter 0 only while int0# pin is high and tr0 bit is set. 2c/t0# timer 0 counter/timer select bit clear for timer operation: timer 0 counts the divided-down system clock. set for counter operation: timer 0 counts negative transitions on external pin t0. 1m10 timer 0 mode select bit m10 m00 operating mode 0 0 mode 0: 8-bit timer/counter (th0) with 5bit prescaler (tl0). 0 1 mode 1: 16-bit timer/counter. 1 0 mode 2: 8-bit auto-reload timer/counter (tl0). (2) 1 1 mode 3: tl0 is an 8-bit timer/counter. th0 is an 8-bit timer using timer 1?s tr0 and tf0 bits. 0 m00 76543210 bit number bit mnemonic description 7:0 high byte of timer 0
61 T89C51CC02 4126f?can?12/03 table 40. tl0 register tl0 (s:8ah) timer 0 low byte register reset value = 0000 0000b table 41. th1 register th1 (s:8dh) timer 1 high byte register reset value = 0000 0000b table 42. tl1 register tl1 (s:8bh) timer 1 low byte register reset value = 0000 0000b 76543210 bit number bit mnemonic description 7:0 low byte of timer 0 76543210 bit number bit mnemonic description 7:0 high byte of timer 1 76543210 bit number bit mnemonic description 7:0 low byte of timer 1
62 T89C51CC02 4126f?can?12/03 timer 2 the T89C51CC02 timer 2 is compatible with timer 2 in the 80c52. it is a 16-bit timer/counter: the count is maintained by two eightbit timer registers, th2 and tl2 that are cascade-connected. it is controlled by t2con register (see table 44) and t2mod register (see table 45). timer 2 operation is similar to timer 0 and timer 1. c/t2 selects f t2 clock /6 (timer operation) or exter nal pin t2 (counter operation) as timer clock. setting tr2 allows tl2 to be incremented by the selected input. timer 2 includes the following enhancements: auto-reload mode (up or down counter) programmable clock-output auto-reload mode the auto-reload mode configures timer 2 as a 16-bit timer or event counter with auto- matic reload. this feature is controlled by the dcen bit in t2mod register (see table 44). setting the dcen bit enables timer 2 to count up or down as shown in figure 29. in this mode the t2ex pin controls the counting direction. when t2ex is high, timer 2 counts up. timer overflow occurs at ffffh which sets the tf2 flag and generates an interrupt request. the overflow also causes the 16-bit value in rcap2h and rcap2l registers to be loaded into the timer registers th2 and tl2. when t2ex is low, timer 2 counts down. timer underflow occurs when the count in the timer registers th2 and tl2 equals the value stored in rcap2h and rcap2l registers. the underflow sets tf2 flag and reloads ffffh into the timer registers. the exf2 bit toggles when timer 2 overflow or underflow, depending on the direction of the count. exf2 does not generate an interrupt. this bit can be used to provide 17-bit resolution. figure 29. auto-reload mode up/down counter (down counting reload value) tf2 t2 exf2 th2 (8-bit) tl2 ( 8-bit) rcap2h (8-bit) rcap2l (8-bit) ffh (8-bit) ffh (8-bit) toggle (up counting reload value) timer 2 interrupt :6 t2con reg t2con reg t2ex: 1=up 2=down 0 1 ct/2 t2con.1 tr2 t2con.2 ft2 clock see section ?clock?
63 T89C51CC02 4126f?can?12/03 programmable clock- output in clock-out mode, timer 2 operates as a 50%-duty-cycle, programmable clock genera- tor (figure 30). the input clock increments tl2 at frequency f osc /2. the timer repeatedly counts to overflow from a loaded value. at overflow, the contents of rcap2h and rcap2l registers are loaded into th2 and tl2. in this mode, timer 2 overflows do not generate interrupts. the formula gives the clock-out frequency depending on the system osc illator frequen cy and the value in the rcap2h and rcap2l registers: for a 16 mhz system clock in x1 mode, timer 2 has a programmable frequency range of 61 hz (f osc /2 16) to 4 mhz (f osc /4). the generated clock signal is brought out to t2 pin (p1.0). timer 2 is programmed for the clock-out mode as follows: set t2oe bit in t2mod register. clear c/t2 bit in t2con register. determine the 16-bit reload value from the formula and enter it in rcap2h/rcap2l registers. enter a 16-bit initial value in timer registers th2/tl2. it can be the same as the reload value or different depending on the application. to start the timer, set tr2 run control bit in t2con register. it is possible to use timer 2 as a baud rate generator and a clock generator simulta- neously. for this configuration, the baud rates and clock frequencies are not independent since both functions use the values in the rcap2h and rcap2l registers. figure 30. clock-out mode clock outfrequency C ft 2 clock 4 65536 rcap 2 h C rcap 2 l ? () ---------------------------------------------------------------------------------------- - = :2 exen2 exf2 overflow t2ex th2 (8-bit) tl2 (8-bit) timer 2 rcap2h (8-bit) rcap2l (8-bit) t2oe t2 t2con reg t2con reg t2mod reg 1 0 c/t2 t2con reg interrupt 0 1 ct/2 t2con.1 tr2 t2con.2 ft2 clock
64 T89C51CC02 4126f?can?12/03 registers table 43. t2con register t2con (s:c8h) timer 2 control register reset value = 0000 0000b bit addressable 76543210 tf2 exf2 rclk tclk exen2 tr2 c/t2# cp/rl2# bit number bit mnemonic description 7tf2 timer 2 overflow flag tf2 is not set if rclk=1 or tclk = 1. must be cleared by software. set by hardware on timer 2 overflow. 6exf2 timer 2 external flag set when a capture or a reload is caused by a negative transition on t2ex pin if exen2=1. set to cause the cpu to vector to timer 2 interrupt routine when timer 2 interrupt is enabled. must be cleared by software. 5rclk receive clock bit clear to use timer 1 overflow as receive clock for serial port in mode 1 or 3. set to use timer 2 overflow as receive clock for serial port in mode 1 or 3. 4tclk transmit clock bit clear to use timer 1 overflow as transmit clock for serial port in mode 1 or 3. set to use timer 2 overflow as transmit clock for serial port in mode 1 or 3. 3 exen2 timer 2 external enable bit clear to ignore events on t2ex pin for timer 2 operation. set to cause a capture or reload when a negative transition on t2ex pin is detected, if timer 2 is not used to clock the serial port. 2tr2 timer 2 run control bit clear to turn off timer 2. set to turn on timer 2. 1c/t2# timer/counter 2 select bit clear for timer operation (input from internal clock system: f osc ). set for counter operation (input from t2 input pin). 0cp/rl2# timer 2 capture/reload bit if rclk=1 or tclk=1, cp/rl2# is ignored and timer is forced to auto-reload on timer 2 overflow. clear to auto-reload on timer 2 overflows or negative transitions on t2ex pin if exen2=1. set to capture on negative transitions on t2ex pin if exen2=1.
65 T89C51CC02 4126f?can?12/03 table 44. t2mod register t2mod (s:c9h) timer 2 mode control register reset value = xxxx xx00b not bit addressable table 45. th2 register th2 (s:cdh) timer 2 high byte register reset value = 0000 0000b not bit addressable 76543210 ------t2oedcen bit number bit mnemonic description 7- reserved the value read from this bit is indeterminate. do not set this bit. 6- reserved the value read from this bit is indeterminate. do not set this bit. 5- reserved the value read from this bit is indeterminate. do not set this bit. 4- reserved the value read from this bit is indeterminate. do not set this bit. 3- reserved the value read from this bit is indeterminate. do not set this bit. 2- reserved the value read from this bit is indeterminate. do not set this bit. 1t2oe timer 2 output enable bit clear to program p1.0/t2 as clock input or i/o port. set to program p1.0/t2 as clock output. 0 dcen down counter enable bit clear to disable timer 2 as up/down counter. set to enable timer 2 as up/down counter. 76543210 -------- bit number bit mnemonic description 7 - 0 high byte of timer 2
66 T89C51CC02 4126f?can?12/03 table 46. tl2 register tl2 (s:cch) timer 2 low byte register reset value = 0000 0000b not bit addressable table 47. rcap2h register rcap2h (s:cbh) timer 2 reload/capture high byte register reset value = 0000 0000b not bit addressable table 48. rcap2l register rcap2l (s:cah) timer 2 reload/capture low byte register reset value = 0000 0000b not bit addressable 76543210 -------- bit number bit mnemonic description 7 - 0 low byte of timer 2 76543210 -------- bit number bit mnemonic description 7 - 0 high byte of timer 2 reload/capture. 76543210 -------- bit number bit mnemonic description 7 - 0 low byte of timer 2 reload/capture.
67 T89C51CC02 4126f?can?12/03 watchdog timer T89C51CC02 contains a powerful programmable hardware watchdog timer (wdt) that automatically resets the chip if it software fails to reset the wdt before the selected time interval has elapsed. it permits large timeout ranging from 16ms to 2s @f osc = 12 mhz in x1 mode. this wdt consists of a 14-bit counter plus a 7-bit programmable counter, a watchdog timer reset register (wdtrst) and a watchdog timer programming (wdtprg) regis- ter. when exiting reset, the wdt is -by default- disable. to enable the wdt, the user has to write the sequence 1eh and e1h into wdtrst register with no instruction between the two writes. when the watchdog timer is enabled, it will increment every machine cycle while the oscillator is running and there is no way to disable the wdt except through reset (either hardware reset or wdt over- flow reset). when wdt overflows, it will generate an output reset pulse at the rst pin. the reset pulse duration is 96xt osc , where t osc =1/f osc . to make the best use of the wdt, it should be serviced in those sections of code that will periodically be exe- cuted within the time required to prevent a wdt reset note: when the watchdog is enable it is impossible to change its period. figure 31. watchdog timer 6 ps cpu and peripheral clock fwd clock wdtprg reset decoder control wdtrst wr enable 14-bit counter 7-bit counter outputs fwd clock reset - - - - - 2 1 0
68 T89C51CC02 4126f?can?12/03 watchdog programming the three lower bits (s0, s1, s2) located into wdtprg register permit to program the wdt duration. table 49. machine cycle count to compute wd timeout, the following formula is applied: note: svalue represents the decimal value of (s2 s1 s0) find hereafter computed timeout values for f osc xtal = 12 mhz in x1 mode table 50. timeout computation s2 s1 s0 machine cycle count 000 2 14 - 1 001 2 15 - 1 010 2 16 - 1 011 2 17 - 1 100 2 18 - 1 101 2 19 - 1 110 2 20 - 1 111 2 21 - 1 s2 s1 s0 f osc =12 mhz f osc =16mhz f osc =20 mhz 0 0 0 16.38 ms 12.28 ms 9.82 ms 0 0 1 32.77 ms 24.57 ms 19.66 ms 0 1 0 65.54 ms 49.14 ms 39.32 ms 0 1 1 131.07 ms 98.28 ms 78.64 ms 1 0 0 262.14 ms 196.56 ms 157.28 ms 1 0 1 524.29 ms 393.12 ms 314.56 ms 1 1 0 1.05 s 786.24 ms 629.12 ms 1 1 1 2.10 s 1.57 s 1.25 ms ftime out f wd 12 2 14 2 svalue () 1 C () ---------------------------------------------------------------- - = C
69 T89C51CC02 4126f?can?12/03 watchdog timer during power-down mode and idle in power-down mode the oscillator stops, which means the wdt also stops. while in power-down mode, the user does not need to service the wdt. there are 2 methods of exiting power-down mode: by a hardware reset or via a level activated external interrupt which is enabled prior to entering power-down mode. when power-down is exited with hardware reset, the watchdog is disabled. exiting power-down with an interrupt is signif- icantly different. the interrupt shall be held low long enough for the os cillator to stabilize. when the interrupt is brought high, the interrupt is serviced. to prevent the wdt from resetting the device while the interrupt pin is held low, the wdt is not started until the interrupt is pulled high. it is suggested that the wdt be reset during the interrupt service for the interrupt used to exit power-down. to ensure that the wdt does not overflow within a few states of exiting powerdown, it is best to reset the wdt just before entering powerdown. in the idle mode, the oscillator cont inues to run. to prevent the wdt from resetting T89C51CC02 while in idle mode, the user shoul d always set up a ti mer that will periodi- cally exit idle, service the wdt, and re-enter idle mode. register table 51. wdtprg register wdtprg (s:a7h) ? watchdog timer duration programming register reset value = xxxx x000b 76543210 - - - - - s2 s1 s0 bit number bit mnemonic description 7- reserved the value read from this bit is indeterminate. do not set this bit. 6- reserved the value read from this bit is indeterminate. do not set this bit. 5- reserved the value read from this bit is indeterminate. do not set this bit. 4- reserved the value read from this bit is indeterminate. do not set this bit. 3- reserved the value read from this bit is indeterminate. do not set this bit. 2s2 watchdog timer duration selection bit 2 work in conjunction with bit 1 and bit 0. 1s1 watchdog timer duration selection bit 1 work in conjunction with bit 2 and bit 0. 0s0 watchdog timer duration selection bit 0 work in conjunction with bit 1 and bit 2.
70 T89C51CC02 4126f?can?12/03 table 52. wdtrst register wdtrst (s:a6h write only) ? watchdog timer enable register reset value = 1111 1111b note: the wdrst register is used to reset/enable the wdt by writing 1eh then e1h in sequence without instruction between these two sequences. 76543210 -------- bit number bit mnemonic description 7 - watchdog control value
71 T89C51CC02 4126f?can?12/03 can controller the can controller provides all the features required to implement the serial communi- cation protocol can as defined by bosch gmbh. the can specification as referred to by iso/11898 (2.0a & 2.0b) for high speed and iso/11519-2 for low speed. the can controller is able to handle all types of frames (data, remote, error and overload) and achieves a bitrate of 1-mbit/s at 8 mhz 1 crystal frequency in x2 mode. note: 1. at brp = 1 sampling point will be fixed. can controller description the can controller accesses are made through sfr. several operations are possible by sfr: arithmetic and logic operations, transfers and program control (sfr is accessible by direct addressing). 4 independent message objects are implemented, a pagination system manages their accesses. any message object can be programmed in a reception buffer block (even non-consec- utive buffers). for the reception of defined messages one or several receiver message objects can be masked without participating in the buffer feature. an it is generated when the buffer is full. the frames following the buffer-full interrupt will not be taken into account until at least one of the buffer message objects is re-enabled in reception. higher priority of a message object for reception or transmission is given to the lower message object number. the programmable 16-bit timer (cantimer) is used to stamp each received and sent message in the canstmp register. this timer starts counting as soon as the can con- troller is enabled by the ena bit in the cangcon register. the time trigger communication (ttc) protocol is supported by the T89C51CC02. figure 32. can controller block diagram bit stuffing /destuffing cyclic redundancy check receive transmit error counter rec/tec bit timing logic page register dpr(mailbox + registers) priority encoder c-core interface core control interface bus txdc rxdc
72 T89C51CC02 4126f?can?12/03 can controller mailbox and registers organization the pagination allows management of the 91 registers including 80(4 x 20) bytes of mailbox via 32 sfrs. all actions on the message object window sfrs apply to the corresponding message object registers pointed by the message object number find in the page message object register (canpage) as illustrate in figure 33. figure 33. can controller memory organization ch.3 - id tag - 1 ch.3 - id tag - 2 ch.3 - id tag - 4 ch.3 - id tag - 3 ch.3 - id mask - 1 ch.3 - id mask - 2 ch.3 - id mask - 4 ch.3 - id mask - 3 ch.3 - message data - byte 0 general control general status bit timing - 1 bit timing - 2 bit timing - 3 enable interrupt enable interrupt message object page message object message object status message object control & dlc message data id tag - 1 id tag - 2 id tag - 4 id tag - 3 id mask - 1 id mask - 2 id mask - 4 id mask - 3 message object 0 - status message object 0 - control & dlc ch.0 - id tag - 1 ch.0 - id tag - 2 ch.0 - id tag - 4 ch.0 - id tag - 3 ch.0 - message data - byte 0 message object 3 - status message object 3 - control & dlc status interrupt message object (message object number) (data offset) sfrs on-chip can controller registers 4 message objects 8 bytes timstmp high timstmp low ch.0 - id mask- 1 ch.0 - id mask- 2 ch.0 - id mask - 4 ch.0 - id mask- 3 cantimer high cantimer low timttc high timttc low tec counter rec counter timer control enable message object message object window sfrs ch.0 timstmp high ch.0 timstmp low ch.3 timstmp high ch.3 timstmp low general interrupt
73 T89C51CC02 4126f?can?12/03 working on message objects the page message object register (canpage) is used to select one of the 4 message objects. then, message object control (canconch) and message object status (canstch) are available for this selected message object number in the corresponding sfrs. a single register (canmsg) is used for the message. the mailbox pointer is managed by the page message object register with an auto-incrementation at the end of each access. the range of this counter is 8. note that the maibox is a pure ram, dedicated to one message object, without overlap. in most cases, it is not necessary to transfer the received message into the standard memory. the message to be transmitted can be built directly in the maibox. most calcu- lations or tests can be executed in the mailbox area which provide quicker access. can controller management in order to enable the can controller correctly the following registers have to be initialized: general control (cangcon), bit timing (canbt 1, 2 & 3), and for each page of 15 message objects: ? message object control (canconch), ? message object status (canstch). during operation, the can enable message object registers (canen) gives a fast over- view of the message objects availability. the can messages can be handled by interrupt or polling modes. a message object can be configured as follows: transmit message object receive message object receive buffer message object disable this configuration is made in the conch field of the canconch register (see table 53). when a message object is configured, the co rresponding ench bit of canen register is set. table 53. configuration for conch1:2 when a transmitter or receiver action of a message object is completed, the corre- sponding ench bit of the canen register is cleared. in order to re-enable the message object, it is necessary to re-write the configuration in canconch register. non-consecutive message objects can be used for all three types of message objects (transmitter, receiver and receiver buffer). conch 1 conch 2 type of message object 00disable 0 1 transmitter 10receiver 1 1 receiver buffer
74 T89C51CC02 4126f?can?12/03 buffer mode any message object can be used to define one buffer, including non-consecutive mes- sage objects, and with no limitation in number of message objects used up to 4. each message object of the buffer must be initialized conch2 = 1 and conch1 = 1; figure 34. buffer mode the same acceptance filter must be defined for each message objects of the buffer. when there is no mask on the identifier or the ide, all messages are accepted. a received frame will always be stor ed in the lowest free message object. when the flag rxok is set on one of the buffer message objects, this message object can then be read by the application. this flag must then be cleared by the software and the message object re-enabled in buffer reception in order to free the message object. the ovrbuf flag in the cangit register is set when the buffer is full. this flag can generate an interrupt. the frames following the buffer-full interrupt will not be stored and no status will be over- written in the canstch registers involved in the buffer until at least one of the buffer message objects is re-enabled in reception. this flag must be cleared by the software in order to acknowledge the interrupt. it can management the different interrupts are: transmission interrupt reception interrupt interrupt on error (bit error, stuff error, crc error, form error, acknowledge error) interrupt when buffer receive is full interrupt on overrun of can timer message object 0 message object 1 message object 2 message object 3 block buffer buffer 0 buffer 1
75 T89C51CC02 4126f?can?12/03 figure 35. can controller interrupt structure to enable a transmission interrupt: enable general can it in the interrupt system register enable interrupt by message object, eichi enable transmission interrupt, entx to enable a reception interrupt: enable general can it in the interrupt system register enable interrupt by message object, eichi enable reception interrupt, enrx to enable an interrupt on message object error: enable general can it in the interrupt system register enable interrupt by message object, eichi enable interrupt on error, enerch to enable an interrupt on general error: enable general can it in the interrupt system register enable interrupt on error, energ sit i i=0 i=4 ovrit enrx cangie.5 entx cangie.4 enerch cangie.3 enbuf cangie.2 ecan ien1.0 rxok i canstch.5 txok i canstch.6 berr i canstch.4 serr i canstch.3 ferr i canstch.1 cerr i canstch.2 aerr i canstch.0 eich i canie ovrtim cangit.5 ovrbuf cangit.4 ferg cangit.1 aerg cangit.0 serg cangit.3 cerg cangit.2 energ cangie.1 etim ien1.2 sit i cansit canit cangit.7 can it
76 T89C51CC02 4126f?can?12/03 to enable an interrupt on buffer-full condition: enable general can it in the interrupt system register enable interrupt on buffer full, enbuf to enable an interrupt when timer overruns: enable overrun it in the interrupt system register when an interrupt occurs, the corresponding message object bit is set in the sit register. to acknowledge an interrupt, the corresponding canstch bits (rxok, txok,...) or cangit bits (ovrtim, ovrbuf,...), must be cleared by the software application. when the can node is in transmission and detects a form error in its frame, a bit error will also be raised. consequently, two consecutive interrupts can occur, both due to the same error. when a message object error occurs and is set in canstch register, no general error are set in cangie register. bit timing and baud rate figure 36. sample and transmission point the baud rate selection is made by tbit calculation: tbit = tsyns + tprs + tphs1 + tphs2 1. tsyns = tscl = (brp[5..0]+ 1)/fcan = 1tq 2. tprs = (1 to 8) * tscl = (prs[2..0]+ 1) * tscl 3. tphs1 = (1 to 8) * tscl = (phs1[2..0]+ 1) * tscl 4. tphs2 = (1 to 8) * tscl = (phs2[2..0]+ 1) * tscl 5. tsjw = (1 to 4) * tscl = (sjw[1..0]+ 1) * tscl the total number of tscl (time quanta) in a bit time must be comprised between 8 to 25. fcan clock prescaler brp prs 3bit length phs1 3bit length phs2 3bit length sjw 2-bit length bit timing system clock tscl time quantum sample point transmission poin t
77 T89C51CC02 4126f?can?12/03 figure 37. general structure of a bit period example of bit timing determination for can baudrate of 500 kbit/s: f osc = 12 mhz in x1 mode => fcan = 6mhz verify that the can baud rate you want is an integer division of fcan clock. fcan/canbaudrate = 6 mhz/500 khz = 12 the time quanta tq must be comprised between 8 and 25: tq = 12 and brp = 0 define the various timing parameters: tbit = tsyns + tprs + tphs1 + tphs2 = 12tq tsyns = 1tq and tsjw =1tq => sjw = 0 if we chose a sample point at 66.6% => tphs2 = 4tq => phs2 = 3 tbit = 12 = 4 + 1 + tphs1 + tprs, let us choose tprs = 3 tphs1 = 4 phs1 = 3 and prs = 2 brp = 0 so canbt1 = 00h sjw = 0 and prs = 2 so canbt2 = 04h phs2 = 3 and phs1 = 3 so canbt3 = 36h bit rate prescaler oscillator 1/ fcan tscl system clock one nominal bit tsyns (*) tprs sample point (*) synchronization segment: syns tbit tsyns = 1xtscl (fixed) data tbit tsyns tprs tphs 1 tphs 2 ++ + = tbit calculation: transmission poi nt tphs1 + tsjw (3) tphs2 - tsjw (4) ( 1) phase error 0 ( 2) phase error 0 ( 3) phase error > 0 ( 4) phase error < 0 tphs2 (2) tphs1 (1)
78 T89C51CC02 4126f?can?12/03 fault confinement with respect to fault confinement, a unit may be in one of the three following status: error active error passive bus off an error active unit takes part in bus communication and can send an active error frame when the can macro detects an error. an error passive unit cannot send an active error frame. it takes part in bus communica- tion, but when an error is detected, a passive error frame is sent. also, after a transmission, an error passive unit will wait before initiating further transmission. a bus off unit is not allowed to have any influence on the bus. for fault confinement, two error counters (tec and rec) are implemented. see can specification for details on fault confinement. figure 38. line error mode tec > 255 error active error passive bus off init. tec < 127 and rec < 127 tec > 127 or rec > 127 128 occurrences of 11 consecutive recessive bit tec : transmit error counter rec : receive error counter
79 T89C51CC02 4126f?can?12/03 acceptance filter upon a reception hit (i.e., a good comparison between the id+rtr+rb+ide received and an id+rtr+rb+ide specified while taking the comparison mask into account) the id+rtr+rb+ide received are writ ten over the id tag registers. id => idt0-29 rtr => rtrtag rb => rb0-1tag ide => ide in canconch register figure 39. acceptance filter block diagram example: to accept only id = 318h in part a. id msk = 111 1111 1111 b id tag = 011 0001 1000 b 13/32 = 13/32 rxdc 13/32 write 13/32 1 hit 13/32 id msk registers ( ch i ) id & rb rtr ide rx shift register ( internal ) id & rb rtr ide enable ( ch i) id tag registers ( ch i ) & canconch id & rb rtr ide
80 T89C51CC02 4126f?can?12/03 data and remote frame description of the different steps for: data frame remote frame, with automatic reply remote frame u u u u u 0 1 x 0 0 u u u u u e n c h r t r r p l v t x o k r x o k 0 1 x 0 0 c u c u u 0 0 x 1 0 u c c u u 0 0 x 0 1 d a t a f r a m e node a node b e n c h r t r r p l v t x o k r x o k message object in reception message object stay in receptio n message object in transmission message object stay in transmission u u u u u 1 1 x 0 0 c u u u c 0 1 x 1 0 u c c u u 0 0 x 0 1 r e m o t e f r a m e d a t a f r a m e u u u u u 1 1 1 0 0 u u u c c 0 1 0 0 0 c u c c u 0 0 0 1 0 e n c h r t r r p l v t x o k r x o k e n c h r t r r p l v t x o k r x o k ( i m m e d i a t e ) message object in reception message object in transmission message object stay in transmission message object in transmission message object in reception message object stay in by can controller by can controller reception u u u u u 1 1 x 0 0 u u u u u e n c h r t r r p l v t x o k r x o k 1 1 0 0 0 c u u u c 0 1 x 1 0 u c c u u 1 0 0 0 1 r e m o t e f r a m e e n c h r t r r p l v t x o k r x o k u u u u u 0 1 x 0 0 c u c u u 0 0 x 1 0 u c c u c 0 0 x 0 1 d a t a f r a m e ( d e f e r r e d ) u : modified by user i c : modified by can i message object in reception message object in transmission by use r message object stay in transmission message object stay in reception message object in transmission message object in reception message object in reception by can controller by user
81 T89C51CC02 4126f?can?12/03 time trigger communication (ttc) and message stamping the T89C51CC02 has a programmable 16-bit timer (cantimh&cantiml) for mes- sage stamp and ttc. this can timer starts after the can controller is enabled by the ena bit in the cang- con register. two modes in the timer are implemented: time trigger communication: ? capture of this timer value in the canttch & canttcl registers on start of frame (sof) or end of frame (eof), depending on the syncttc bit in the cangcon register, when the network is configured in ttc by the ttc bit in the cangcon register. note: in this mode, can only sends the frame once, even if an error occurs . message stamping ? capture of this timer value in the canstmph & canstmpl registers of the message object which received or sent the frame. ? all messages can be stamps. ? the stamping of a received frame occurs when the rxok flag is set. ? the stamping of a sent frame occurs when the txok flag is set. the can timer works in a roll-over from ffffh to 0000h which serves as a time base. when the timer roll-over from ffffh to 0000h, an interrupt is generated if the etim bit in the interrupt enable register ien1 is set. figure 40. block diagram of can timer eof on can frame ena cangcon.1 cantcon rxok i canstch.5 txok i canstch.4 6 fcan clock sof on can frame ttc cangcon.5 syncttc cangcon.4 canttch & canttcl canstmph & canstmpl cantimh & cantiml ovrtim cangit.5 when 0xffff to 0x0000
82 T89C51CC02 4126f?can?12/03 can autobaud and listening mode to activate the autobaud feature, the autobaud bit in the cangcon register must be set. in this mode, the can controller is only listening to the line without acknowledg- ing the received messages. it cannot send any message. the error flags are updated. the bit timing can be adjusted until no error occurs (good configuration find). in this mode, the error counters are frozen. to go back to the standard mode, the autobaud bit must be cleared. figure 41. autobaud mode routine examples 1. init of can macro // reset the can macro cangcon = 01h; // disable can interrupts ecan = 0; etim = 0; // init the mailbox for num_page =0; num_page <4; num_page++ { canpage = num_channel << 4; canconch = 00h canstch = 00h; canidt1 = 00h; canidt2 = 00h; canidt3 = 00h; canidt4 = 00h; canidm1 = 00h; canidm2 = 00h; canidm3 = 00h; canidm4 = 00h; for num_data =0; num_data <8; num_data++) { canmsg = 00h; } } // configure the bit timing canbt1 = xxh canbt2 = xxh canbt3 = xxh 0 1 txdc rxdc autobaud cangcon.3 rxdc txdc
83 T89C51CC02 4126f?can?12/03 // enable the can macro cangcon = 02h 2. configure message object 3 in reception to receive only standard (11bit identifier) message 100h // select the message object 3 canpage = 30h // enable the interrupt on this message object canie = 08h // clear the status and control register canstch = 00h canconch= 00h // init the acceptance filter to accept only message 100h in standard mode canidt1 = 20h canidt2 = 00h canidt3 = 00h canidt4 = 00h canidm1 = ffh canidm2 = ffh canidm3 = ffh canidm4 = ffh // enable channel in reception canconch = 88h // enable reception note: to enable the can interrupt in reception: ea = 1 ecan = 1 cangie = 20h 3. send a message on the message object 0 // select the message object 0 canpage = 00h // enable the interrupt on this message object canie = 01h // clear the status register canstch = 00h; // load the identifier to send (ex: 555h) canidt1 = aah; canidt2 = a0h; // load data to send canmsg = 00h canmsg = 01h canmsg = 02h canmsg = 03h canmsg = 04h canmsg = 05h canmsg = 06h canmsg = 07h // configure the control register canconch = 18h 4. interrupt routine // save the current canpage
84 T89C51CC02 4126f?can?12/03 // find the first message object which generate an interrupt in cansit // select the corresponding message object // analyse the canstch register to identify which kind of interrupt is generated // manage the interrupt // clear the status register canstch = 00h; // if it is not a channel interrupt but a general interrupt // manage the general interrupt and clear cangit register // restore the old canpage
85 T89C51CC02 4126f?can?12/03 can sfrs table 54. sfr mapping 0/8 (1) 1/9 2/a 3/b 4/c 5/d 6/e 7/f f8h ipl1 xxxx x000 ch 0000 0000 ccap0h 0000 0000 ccap1h 0000 0000 ffh f0h b 0000 0000 adclk xxx0 0000 adcon x000 0000 addl 0000 0000 addh 0000 0000 adcf 0000 0000 iph1 xxxx x000 f7h e8h ien1 xxxx x000 cl 0000 0000 ccap0l 0000 0000 ccap1l 0000 0000 efh e0h acc 0000 0000 e7h d8h ccon 0000 0000 cmod 0xxx x000 ccapm0 x000 0000 ccapm1 x000 0000 dfh d0h psw 0000 0000 fcon 0000 0000 eecon xxxx xx00 d7h c8h t2con 0000 0000 t2mod xxxx xx00 rcap2l 0000 0000 rcap2h 0000 0000 tl2 0000 0000 th2 0000 0000 canen xxxx 0000 cfh c0h p4 xxxx xx11 cangie 1100 0000 canie 1111 0000 canidm1 xxxx xxxx canidm2 xxxx xxxx canidm3 xxxx xxxx canidm4 xxxx xxxx c7h b8h ipl0 x000 0000 saden 0000 0000 cansit xxxx 0000 canidt1 xxxx xxxx canidt2 xxxx xxxx canidt3 xxxx xxxx canidt4 xxxx xxxx bfh b0h p3 1111 1111 canpage 1100 0000 canstch xxxx xxxx canconch xxxx xxxx canbt1 xxxx xxxx canbt2 xxxx xxxx canbt3 xxxx xxxx iph0 x000 0000 b7h a8h ien0 0000 0000 saddr 0000 0000 cangsta 1010 0000 cangcon 0000 0000 cantiml 0000 0000 cantimh 0000 0000 canstmpl xxxx xxxx canstmph xxxx xxxx afh a0h p2 xxxx xx11 cantcon 0000 0000 auxr1 (2) xxxx 00x0 canmsg xxxx xxxx canttcl 0000 0000 canttch 0000 0000 wdtrst 1111 1111 wdtprg xxxx x000 a7h 98h scon 0000 0000 sbuf 0000 0000 cangit 0x00 0000 cantec 0000 0000 canrec 0000 0000 9fh 90h p1 1111 1111 97h 88h tcon 0000 0000 tmod 0000 0000 tl0 0000 0000 tl1 0000 0000 th0 0000 0000 th1 0000 0000 ckcon 0000 0000 8fh 80h sp 0000 0111 dpl 0000 0000 dph 0000 0000 pcon 00x1 0000 87h 0/8 (1) 1/9 2/a 3/b 4/c 5/d 6/e 7/f
86 T89C51CC02 4126f?can?12/03 registers table 55. cangcon register cangcon (s:abh) can general control register reset value = 0000 0000b 7654 3210 abrq ovrq ttc syncttc autobaud test ena gres bit number bit mnemonic description 7 abrq abort request not an auto-resetable bit. a reset of the ench bit (message object control & dlc register) is done for each message object. the pending transmission communications are immediately aborted but the on-going communication will be terminated normally, setting the appropriate status flags, txok or rxok. 6ovrq overload frame request (initiator) . auto-resetable bit. set to send an overload frame after the next received message. cleared by the hardware at the beginning of transmission of the overload frame. 5ttc network in timer trigger communication set to select node in ttc. clear to disable ttc features. 4 syncttc synchronization of ttc when this bit is set the ttc timer is caught on the last bit of the end of frame. when this bit is clear the ttc timer is caught on the start of frame. this bit is only used in the ttc mode. 3autobaud autobaud set to active listening mode. clear to disable listening mode 2test test mode. the test mode is intended for factory testing and not for customer use. 1ena/stb enable/standby can controller when this bit is set, it enables the can controller and its input clock. when this bit is clear, the on-going communication is terminated normally and the can controller state of the machine is frozen (the ench bit of each message object does not change). in the standby mode, the transmitter constantly provides a recessive level; the receiver is not activated and the input clock is stopped in the can controller. during the disable mode, the registers and the mailbox remain accessible. note that two clock periods are needed to start the can controller state of the machine. 0gres general reset (software reset). auto-resetable bit. this reset command is ?ored? with the hardware reset in order to reset the controller. after a reset, the controller is disabled.
87 T89C51CC02 4126f?can?12/03 table 56. cangsta register cangsta (s:aah) can general status register note: 1. these fields are read only. reset value = x0x0 0000b 76543210 - ovfg - tbsy rbsy enfg boff errp bit number bit mnemonic description 7- reserved the values read from this bit is indeterminate. do not set this bit. 6ovfg overload frame flag (1) this status bit is set by the hardware as long as the produced overload frame is sent. this flag does not generate an interrupt 5- reserved the values read from this bit is indeterminate. do not set this bit. 4 tbsy transmitter busy (1) this status bit is set by the hardware as long as the can transmitter generates a frame (remote, data, overload or error frame) or an ack field. this bit is also active during an interframe spacing if a frame must be sent. this flag does not generate an interrupt. 3rbsy receiver busy (1) this status bit is set by the hardware as long as the can receiver acquires or monitors a frame. this flag does not generate an interrupt. 2enfg enable on-chip can controller flag (1) because an enable/disable command is not effective immediately, this status bit gives the true state of a chosen mode. this flag does not generate an interrupt. 1boff bus off mode (1) see figure 38 0 errp error passive mode (1) see figure 38
88 T89C51CC02 4126f?can?12/03 table 57. cangit register cangit (s:9bh) can general interrupt note: 1. these fields are read only. reset value = 0x00 0000b 76543210 canit - ovrtim ovrbuf serg cerg ferg aerg bit number bit mnemonic description 7canit general interrupt flag (1) this status bit is the image of all the can controller interrupts sent to the interrupt controller. it can be used in the case of the polling method. 6- reserved the values read from this bit is indeterminate. do not set this bit. 5ovrtim overrun can timer this status bit is set when the can timer switches 0xffff to 0x0000. if the bit etim in the ie1 register is set, an interrupt is generated. clear this bit in order to reset the interrupt. 4 ovrbuf overrun buffer 0 - no interrupt. 1 - it turned on this bit is set when the buffer is full. bit resetable by user. see figure 35. 3 serg stuff error general detection of more than five consecutive bits with the same polarity. this flag can generate an interrupt. resetable by user. 2cerg crc error general the receiver performs a crc check on each destuffed received message from the start of frame up to the data field. if this checking does not match with the destuffed crc field, a crc error is set. this flag can generate an interrupt. resetable by user. 1ferg form error general the form error results from one or more violations of the fixed form in the following bit fields: crc delimiter acknowledgment delimiter end_of_frame this flag can generate an interrupt. resetable by user. 0 aerg acknowledgment error general no detection of the dominant bit in the acknowledge slot. this flag can generate an interrupt. resetable by user.
89 T89C51CC02 4126f?can?12/03 table 58. cantec register cantec (s:9ch read only) ? can transmit error counter reset value = 00h table 59. canrec register canrec (s:9dh read only) ? can reception error counter reset value = 00h 76543210 tec7 tec6 tec5 tec4 tec3 tec2 tec1 tec0 bit number bit mnemonic description 7 - 0 tec7:0 transmit error counte r see figure 38 76543210 rec7 rec6 rec5 rec4 rec3 rec2 rec1 rec0 bit number bit mnemonic description 7 - 0 rec7:0 reception error counter see figure 38
90 T89C51CC02 4126f?can?12/03 table 60. cangie register cangie (s:c1h) ? can reset value = xx00 000xb 76543210 - - enrx entx enerch enbuf energ - bit number bit mnemonic description 7 - 6 - reserved the values read from these bits are indeterminate. do not set these bits. 5 enrx enable receive interrupt 0 - disable 1 - enable 4entx enable transmit interrupt 0 - disable 1 - enable 3 enerch enable message object error interrupt 0 - disable 1 - enable 2enbuf enable buf interrupt 0 - disable 1 - enable 1 energ enable general error interrupt 0 - disable 1 - enable 0- reserved the value read from this bit is indeterminate. do not set this bit. see figure 35.
91 T89C51CC02 4126f?can?12/03 table 61. canen register canen (s:cfh read only) can enable message object registers 2 reset value = xxxx 0000b table 62. cansit register cansit (s:bbh read only) ? can status interrupt message object registers 2 reset value = xxxx0000b 76543210 - - - - ench3 ench2 ench1 ench0 bit number bit mnemonic description 7 - 4 - reserved the values read from these bits are indeterminate. do not set these bits. 3 - 0 ench3:0 enable message object 0 - message object is disabled => the message object is free for a new emission or reception. 1 - message object is enabled. this bit is resetable by re-writing the canconch of the corresponding message object. 76543210 - - - - sit3 sit2 sit1 sit0 bit number bit mnemonic description 7 - 4 - reserved the values read from these bits are indeterminate. do not set these bits. 3 - 0 sit3:0 status of interrupt by message object 0 - no interrupt. 1 - it turned on. reset when interrupt condition is cleared by user. sit3:0 = 0b 0000 1001 -> it?s on message objects 3 & 0. see figure 35.
92 T89C51CC02 4126f?can?12/03 table 63. canie register canie (s:c3h) ? can enable interrupt message object registers 2 reset value = xxxx 0000b table 64. canbt1 register canbt1 (s:b4h) ? can bit timing registers 1 note: 1. the can controller bit timing registers must be accessed only if the can controller is disabled with the ena bit of the cangcon register set to 0. see figure 37. no default value after reset. 76543210 - - - - iech 3 iech 2 iech 1 iech 0 bit number bit mnemonic description 7 - 4 - reserved the values read from these bits are indeterminate. do not set these bits. 3 - 0 iech3:0 enable interrupt by message object 0 - disable it. 1 - enable it. iech3:0 = 0b 0000 1100 -> enable it?s of message objects 3 & 2. 76543210 - brp 5 brp 4 brp 3 brp 2 brp 1 brp 0 - bit number bit mnemonic description 7- reserved the value read from this bit is indeterminate. do not set this bit. 6 - 1 brp5:0 baud rate prescaler the period of the can controller system clock tscl is programmable and determines the individual bit timing. (1) 0- reserved the value read from this bit is indeterminate. do not set this bit. ts c l = brp[5..0] + 1 f can
93 T89C51CC02 4126f?can?12/03 table 65. canbt2 register canbt2 (s:b5h) ? can bit timing registers 2 note: 1. the can controller bit timing registers must be accessed only if the can controller is disabled with the ena bit of the cangcon register set to 0. see figure 37. no default value after reset. 76543210 - sjw 1 sjw 0 - prs 2 prs 1 prs 0 - bit number bit mnemonic description 7- reserved the value read from this bit is indeterminate. do not set this bit. 6 - 5 sjw1:0 re-synchronization jump width to compensate for phase shifts between clock oscillators of different bus controllers, the controller must re-synchronize on any relevant signal edge of the current transmission. the synchronization jump width defines the maximum number of clock cycles. a bit period may be shortened or lengthened by a re- synchronization. 4- reserved the value read from this bit is indeterminate. do not set this bit. 3 - 1 prs2:0 programming time segment this part of the bit time is used to compensate for the physical delay times within the network. it is twice the sum of the signal propagation time on the bus line, the input comparator delay and the output driver delay. 0- reserved the value read from this bit is indeterminate. do not set this bit. tsjw = tscl x (sjw [1..0] +1) tprs = tscl x (prs[2..0] + 1)
94 T89C51CC02 4126f?can?12/03 table 66. canbt3 register canbt3 (s:b6h) can bit timing registers 3 note: 1. the can controller bit timing registers must be accessed only if the can controller is disabled with the ena bit of the cangcon register set to 0. see figure 37. no default value after reset. 76543210 - phs2 2 phs2 1 phs2 0 phs1 2 phs1 1 phs1 0 smp bit number bit mnemonic description 7- reserved the value read from this bit is indeterminate. do not set this bit. 6 - 4 phs2 2:0 phase segment 2 this phase is used to compensate for phase edge errors. this segment can be shortened by the re-synchronization jump width. 3 - 1 phs1 2:0 phase segment 1 this phase is used to compensate for phase edge errors. this segment can be lengthened by the re-synchronization jump width. 0smp sample type 0 - once, at the sample point. 1 - three times, the threefold sampling of the bus is the sample point and twice over a distance of a 1/2 period of the tscl. the result corresponds to the majority decision of the three values. tphs2 = tscl x (phs2[2..0] + 1) tphs1 = tscl x (phs1[2..0] + 1)
95 T89C51CC02 4126f?can?12/03 table 67. canpage register canpage (s:b1h) ? can message object page register reset value = xx00 0000b table 68. canconch register canconch (s:b3h) ? can message object control and dlc register no default value after reset 76543210 - - chnb 1 chnb 0 ainc indx2 indx1 indx0 bit number bit mnemonic description 7 - 6 - reserved the values read from these bits are indeterminate. do not set these bits. 5 - 4 chnb3:0 selection of message object number the available numbers are: 0 to 3(see figure 33). 3ainc auto increment of the index (active low) 0 - auto-increment of the index (default value). 1 - non-auto-increment of the index. 2 - 0 indx2:0 index byte location of the data field for the defined message object (see figure 33). 76543210 conch 1 conch 0 rplv ide dlc 3 dlc 2 dlc 1 dlc 0 bit number bit mnemonic description 7 - 6 conch1:0 configuration of message object conch1 conch0 0 0: disable 0 1: launch transmission 1 0: enable reception 1 1: enable reception buffer note: the user must re-write the configuration to enable the corresponding bit in the canen1:2 registers. 5rplv reply valid used in the automatic reply mode after receiving a remote frame 0 - reply not ready. 1 - reply ready & valid. 4ide identifier extension 0 - can standard rev 2.0 a (ident = 11 bits). 1 - can standard rev 2.0 b (ident = 29 bits). 3 - 0 dlc3:0 data length code number of bytes in the data field of the message. the range of dlc is from 0 up to 8. this value is updated when a frame is received (data or remote frame). if the expected dlc differs from the incoming dlc, a warning appears in the canstch register.
96 T89C51CC02 4126f?can?12/03 table 69. canstch register canstch (s:b2h) ? can message object status register note: see figure 35. no default value after reset. 76543210 dlcw txok rxok berr serr cerr ferr aerr bit number bit mnemonic description 7dlcw data length code warning the incoming message does not have the dlc expected. whatever the frame type, the dlc field of the canconch register is updated by the received dlc. 6txok transmit ok the communication enabled by transmission is completed. when the controller is ready to send a frame, if two or more message objects are enabled as producers, the lower index message object (0 to 13) is supplied first. must be cleared by software. this flag can generate an interrupt. 5rxok receive ok the communication enabled by reception is completed. in the case of two or more message object reception hits, the lower index message object (0 to 13) is updated first. must be cleared by software. this flag can generate an interrupt. 4berr bit error (only in transmission) the bit value monitored is different from the bit value sent. exceptions: the monitored recessive bit sent as a dominant bit during the arbitration field and the acknowledge slot detecting a dominant bit during the sending of an error frame. must be cleared by software. this flag can generate an interrupt. 3serr stuff error detection of more than five consecutive bits with the same polarity. must be cleared by software. this flag can generate an interrupt. 2cerr crc error the receiver performs a crc check on each destuffed received message from the start of frame up to the data field. if this checking does not match with the destuffed crc field, a crc error is set. must be cleared by software. this flag can generate an interrupt. 1ferr form error the form error results from one or more violations of the fixed form in the following bit fields: crc delimiter acknowledgment delimiter end_of_frame must be cleared by software. this flag can generate an interrupt. 0aerr acknowledgment error no detection of the dominant bit in the acknowledge slot. must be cleared by software. this flag can generate an interrupt.
97 T89C51CC02 4126f?can?12/03 table 70. canidt1 register for v2.0 part a canidt1 for v2.0 part a (s:bch) ? can identifier tag registers 1 no default value after reset. table 71. canidt2 register for v2.0 part a canidt2 for v2.0 part a (s:bdh) ? can identifier tag registers 2 no default value after reset. table 72. canidt3 register for v2.0 part a canidt3 for v2.0 part a (s:beh) ?can identifier tag registers 3 no default value after reset. 76543210 idt 10 idt 9 idt 8 idt 7 idt 6 idt 5 idt 4 idt 3 bit number bit mnemonic description 7 - 0 idt10:3 identifier tag value see figure 39. 76543210 idt 2 idt 1 idt 0 - - - - - bit number bit mnemonic description 7 - 5 idt2:0 identifier tag value see figure 39. 4-0 - reserved the values read from these bits are indeterminate. do not set these bits. 76543210 -------- bit number bit mnemonic description 7 - 0 - reserved the values read from these bits are indeterminate. do not set these bits.
98 T89C51CC02 4126f?can?12/03 table 73. canidt1 for v2.0 part a canidt4 for v2.0 part a (s:bfh) can identifier tag registers 4 no default value after reset. table 74. canidt2register for v2.0 part a canidt1 for v2.0 part b (s:bch) can identifier tag registers 1 no default value after reset. table 75. canidt2 register for v2.0 part b canidt2 for v2.0 part b (s:bdh) can identifier tag registers 2 no default value after reset. 76543210 - - - - - rtrtag - rb0tag bit number bit mnemonic description 7 - 3 - reserved the values read from these bits are indeterminate. do not set these bits. 2 rtrtag remote transmission request tag value. 1- reserved the values read from this bit are indeterminate. do not set these bit. 0 rb0tag reserved bit 0 tag value. 76543210 idt 28 idt 27 idt 26 idt 25 idt 24 idt 23 idt 22 idt 21 bit number bit mnemonic description 7 - 0 idt28:21 identifier tag value see figure 39. 76543210 idt 20 idt 19 idt 18 idt 17 idt 16 idt 15 idt 14 idt 13 bit number bit mnemonic description 7 - 0 idt20:13 identifier tag value see figure 39.
99 T89C51CC02 4126f?can?12/03 table 76. canidt3 register for v2.0 part b canidt3 for v2.0 part b (s:beh) can identifier tag registers 3 no default value after reset. table 77. canidt4 register for v2.0 part b canidt4 for v2.0 part b (s:bfh) can identifier tag registers 4 no default value after reset. 76543210 idt 12 idt 11 idt 10 idt 9 idt 8 idt 7 idt 6 idt 5 bit number bit mnemonic description 7 - 0 idt12:5 identifier tag value see figure 39. 76543210 idt 4 idt 3 idt 2 idt 1 idt 0 rtrtag rb1tag rb0tag bit number bit mnemonic description 7 - 3 idt4:0 identifier tag value see figure 39. 2rtrtag remote transmission request tag value 1 rb1tag reserved bit 1 tag value. 0 rb0tag reserved bit 0 tag value.
100 T89C51CC02 4126f?can?12/03 table 78. canidm1 register for v2.0 part a canidm1 for v2.0 part a (s:c4h) can identifier mask registers 1 no default value after reset. table 79. canidm2 register for v2.0 part a canidm2 for v2.0 part a (s:c5h) can identifier mask registers 2 no default value after reset. table 80. canidm3 register for v2.0 part a canidm3 for v2.0 part a (s:c6h) can identifier mask registers 3 no default value after reset. 76543210 idmsk 10 idmsk 9 idmsk 8 idmsk 7 idmsk 6 idmsk 5 idmsk 4 idmsk 3 bit number bit mnemonic description 7 - 0 idtmsk10:3 identifier mask value 0 - comparison true forced. 1 - bit comparison enabled. see figure 39. 76543210 idmsk 2 idmsk 1 idmsk 0 - - - - - bit number bit mnemonic description 7 - 5 idtmsk2:0 identifier mask value 0 - comparison true forced. 1 - bit comparison enabled. see figure 39. 4 -0 - reserved the values read from these bits are indeterminate. do not set these bits. 76543210 -------- bit number bit mnemonic description 7 - 0 - reserved the values read from these bits are indeterminate.
101 T89C51CC02 4126f?can?12/03 table 81. canidm4 register for v2.0 part a canidm4 for v2.0 part a (s:c7h) can identifier mask registers 4 note: the id mask is only used for reception. no default value after reset. table 82. canidm1 register for v2.0 part b canidm1 for v2.0 part b (s:c4h) can identifier mask registers 1 note: the id mask is only used for reception. no default value after reset. 76543210 - - - - - rtrmsk - idemsk bit number bit mnemonic description 7 - 3 - reserved the values read from these bits are indeterminate. do not set these bits. 2rtrmsk remote transmission request mask value 0 - comparison true forced. 1 - bit comparison enabled. 1- reserved the value read from this bit is indeterminate. do not set this bit. 0idemsk identifier extension mask value 0 - comparison true forced. 1 - bit comparison enabled. 76543210 idmsk 28 idmsk 27 idmsk 26 idmsk 25 idmsk 24 idmsk 23 idmsk 22 idmsk 21 bit number bit mnemonic description 7 - 0 idmsk28:21 identifier mask value 0 - comparison true forced. 1 - bit comparison enabled. see figure 39.
102 T89C51CC02 4126f?can?12/03 table 83. canidm2 register for v2.0 part b canidm2 for v2.0 part b (s:c5h) can identifier mask registers 2 note: 1. the id mask is only used for reception. no default value after reset. table 84. canidm3 register for v2.0 part b canidm3 for v2.0 part b (s:c6h) can identifier mask registers 3 note: the id mask is only used for reception. no default value after reset. 76543210 idmsk 20 idmsk 19 idmsk 18 idmsk 17 idmsk 16 idmsk 15 idmsk 14 idmsk 13 bit number bit mnemonic description 7 - 0 idmsk20:13 identifier mask value (1) 0 - comparison true forced. 1 - bit comparison enabled. see figure 39. 76543210 idmsk 12 idmsk 11 idmsk 10 idmsk 9 idmsk 8 idmsk 7 idmsk 6 idmsk 5 bit number bit mnemonic description 7 - 0 idmsk12:5 identifier mask value 0 - comparison true forced. 1 - bit comparison enabled. see figure 39.
103 T89C51CC02 4126f?can?12/03 table 85. canidm4 register for v2.0 part b canidm4 for v2.0 part b (s:c7h) can identifier mask registers 4 note: the id mask is only used for reception. no default value after reset. table 86. canmsg register canmsg (s:a3h) can message data register no default value after reset. 76543210 idmsk 4 idmsk 3 idmsk 2 idmsk 1 idmsk 0 rtrmsk - idemsk bit number bit mnemonic description 7 - 3 idmsk4:0 identifier mask value 0 - comparison true forced. 1 - bit comparison enabled. see figure 39. 2rtrmsk remote transmission request mask value 0 - comparison true forced. 1 - bit comparison enabled. 1- reserved the value read from this bit is indeterminate. do not set this bit. 0idemsk identifier extension mask value 0 - comparison true forced. 1 - bit comparison enabled. 76543210 msg 7 msg 6 msg 5 msg 4 msg 3 msg 2 msg 1 msg 0 bit number bit mnemonic description 7 - 0 msg7:0 message data this register contains the mailbox data byte pointed at the page message object register. after writing in the page message object register, this byte is equal to the specified message location (in the mailbox) of the pre- defined identifier + index. if auto-incrementation is used, at the end of the data register writing or reading cycle, the mailbox pointer is auto-incremented. the range of the counting is 8 with no end loop (0, 1,..., 7, 0,...)
104 T89C51CC02 4126f?can?12/03 table 87. cantcon register cantcon (s:a1h) can timer clockcontrol reset value = 00h table 88. cantimh register cantimh (s:adh read only) can timer high reset value = 0000 0000b table 89. cantiml register cantiml (s:ach read only) can timer low reset value = 0000 0000b 76543210 tpresc 7 tpresc 6 tpresc 5 tpresc 4 tpresc 3 tpresc 2 tpresc 1 tpresc 0 bit number bit mnemonic description 7 - 0 tpresc7:0 timer prescaler of can timer this register is a prescaler for the main timer upper counter range = 0 to 255. see figure 40. 76543210 cangtim 15 cangtim 14 cangtim 13 cangtim 12 cangtim 11 cangtim 10 cangtim 9 cangtim 8 bit number bit mnemonic description 7 - 0 cangtim15:8 high byte of message timer see figure 40. 76543210 cangtim 7 cangtim 6 cangtim 5 cangtim 4 cangtim 3 cangtim 2 cangtim 1 cangtim 0 bit number bit mnemonic description 7 - 0 cangtim7:0 low byte of message timer see figure 40.
105 T89C51CC02 4126f?can?12/03 table 90. canstmph register canstmph (s:afh read only) can stamp timer high no default value after reset table 91. canstmpl register canstmpl (s:aeh read only) can stamp timer low no default value after reset table 92. canttch register canttch (s:a5h read only) can ttc timer high reset value = 0000 0000b table 93. canttcl register canttcl (s:a4h read only) can ttc timer low reset value = 0000 0000b 76543210 timstmp 15 timstmp 14 timstmp 13 timstmp 12 timstmp 11 timstmp 10 timstmp 9 timstmp 8 bit number bit mnemonic description 7 - 0 timstmp15:8 high byte of time stamp see figure 40. 76543210 timstmp 7 timstmp 6 timstmp 5 timstmp 4 timstmp 3 timstmp 2 timstmp 1 timstmp 0 bit number bit mnemonic description 7 - 0 timstmp7:0 low byte of time stamp see figure 40. 76543210 timttc 15 timttc 14 timttc 13 timttc 12 timttc 11 timttc 10 timttc 9 timttc 8 bit number bit mnemonic description 7 - 0 timttc15:8 high byte of ttc timer see figure 40. 76543210 timttc 7 timttc 6 timttc 5 timttc 4 timttc 3 timttc 2 timttc 1 timttc 0 bit number bit mnemonic description 7 - 0 timttc7:0 low byte of ttc timer see figure 40.
106 T89C51CC02 4126f?can?12/03 programmable counter array (pca) the pca provides more timing capabilities with less cpu intervention than the standard timer/counters. its advantages include reduced software overhead and improved accu- racy. the pca consists of a dedicated timer/counter which serves as the time base for an array of two compare/capture modules. its clock input can be programmed to count any of the following signals: pca clock frequency/6 (see ?clock? section) pca clock frequency/2 timer 0 overflow external input on eci (p1.2) each compare/capture modules can be programmed in any one of the following modes: rising and/or falling edge capture, software timer high-speed output pulse width modulator when the compare/capture modules are programmed in capture mode, software timer, or high speed output mode, an interrupt can be generated when the module executes its function. both modules and the pca timer overflow share one interrupt vector. the pca timer/counter and compare/capture modules share port 1 for external i/os. these pins are listed below. if the pin is not used for the pca, it can still be used for standard i/o. pca timer the pca timer is a common time base for both modules (see figure 9). the timer count source is determined from the cps1 and cps0 bits in the cmod sfr (see table 8) and can be programmed to run at: 1/6 the pca clock frequency. 1/2 the pca clock frequency. the timer 0 overflow. the input on the eci pin (p1.2). pca component external i/o pin 16-bit counter p1.2/eci 16-bit module 0 p1.3/cex0 16-bit module 1 p1.4/cex1
107 T89C51CC02 4126f?can?12/03 figure 42. pca timer/counter the cmod register includes three additional bits associated with the pca. the cidl bit which allows the pca to stop during idle mode. the ecf bit which when set causes an interrupt and the pca overflow flag cf in ccon register to be set when the pca timer overflows. the ccon register contains the run control bit for the pca and the flags for the pca timer and each module. the cr bit must be set to run the pca. the pca is shut off by clearing this bit. the cf bit is set when the pca counter overflows and an interrupt will be generated if the ecf bit in cmod register is set. the cf bit can only be cleared by software. the ccf0:1 bits are the flags for the modules (ccf0 for module0...) and are set by hardware when either a match or a captur e occurs. these flags also can be cleared by software. cidl cps1 cps0 ecf it ch cl 16-bit up counter to pca modules fpca/6 fpca/2 t0 ovf p1.2 idle cmod 0xd9 cf cr ccon 0xd8 ccf1 ccf0 overflow
108 T89C51CC02 4126f?can?12/03 pca modules each one of the two compare/capture modules has six possible functions. it can perform: 16-bit capture, positive-edge triggered 16-bit capture, negative-edge triggered 16-bit capture, both positive and negative-edge triggered 16-bit software timer 16-bit high speed output 8-bit pulse width modulator. each module in the pca has a special function register associated with it (ccapm0 for module 0 ...). the ccapm0:1 registers contain the bits that control the mode that each module will operate in. the eccf bit enables the ccf flag in the ccon register to generate an interrupt when a match or compare occurs in the associated module. the pwm bit enables the pulse width modulation mode. the tog bit when set causes the cex output associated with the module to toggle when there is a match between the pca counter and the module?s capture/compare register. the match bit mat when set will cause the ccfn bit in the ccon register to be set when there is a match between the pca counter and the module?s capture/compare register. the two bits capn and capp in ccapmn register determine the edge that a capture input will be active on. the capn bit enables the negative edge, and the capp bit enables the positive edge. if both bits are set both edges will be enabled. the bit ecom in ccapm register when set enables the comparator function.
109 T89C51CC02 4126f?can?12/03 pca interrupt figure 43. pca interrupt system pca capture mode to use one of the pca modules in capture mode either one or both of the ccapm bits capn and capp for that module must be set. the external cex input for the module (on port 1) is sampled for a transition. when a valid transition occurs the pca hardware loads the value of the pca counter registers (ch and cl) into the module?s capture reg- isters (ccapnl and ccapnh). if the ccfn bit for the module in the ccon sfr and the eccfn bit in the ccapmn sfr are set then an interrupt will be generated. figure 44. pca capture mode cf cr ccon 0xd8 ccf1 ccf0 module 1 module 0 pca timer/counter to interrupt ec ien0.6 ea ien0.7 ecf cmod.0 eccfn ccapmn.0 cexn n = 0, 1 pca counter ch (8-bits) cl (8-bits) ccapnh ccapnl ccfn ccon reg pca interrup t reques t - 0cappncapnn000eccfn 7 ccapmn register (n = 0, 1) 0
110 T89C51CC02 4126f?can?12/03 16-bit software timer mode the pca modules can be used as software timers by setting both the ecom and mat bits in the modules ccapmn register. the pca timer will be compared to the module?s capture registers and when a match occurs an interrupt will occur if the ccfn (ccon sfr) and the eccfn (ccapmn sfr) bits for the module are both set. figure 45. pca 16-bit software timer and high speed output mode ccapnl (8 bits) ccapnh (8 bits) - ecomn0 0 matn togn0 eccfn 70 ccapmn register (n = 0, 1) cl (8 bits) 16-bit comparator match enable ccfn ccon reg pca interrupt request cexn compare/capture module pca counter ?0? ?1? reset write to ccapnl write to ccapnh for software timer mode, set ecomn and matn. for high speed output mode, set ecomn, matn and togn. toggle ch (8 bits)
111 T89C51CC02 4126f?can?12/03 high speed output mode in this mode the cex output (on port 1) associated with the pca module will toggle each time a match occurs between the pca counter and the module?s capture registers. to activate this mode the tog, mat, and ecom bits in the module?s ccapmn sfr must be set. figure 46. pca high speed output mode pulse width modulator mode all the pca modules can be used as pwm outputs. the output frequency depends on the source for the pca timer. all the modules will have the same output frequency because they all share the pca timer. the duty cycl e of each module is independently variable using the module?s capture register ccapln. when the value of the pca cl sfr is less than the value in the module?s ccapln sfr the output will be low, when it is equal to or greater than it, the output will be high. when cl overflows from ff to 00, ccapln is reloaded with the value in ccaphn. the allows the pwm to be updated with- out glitches. the pwm and ecom bits in the module?s ccapmn register must be set to enable the pwm mode. ch cl ccapnh ccapnl ecomn ccapmn, n = 0 to 1 0xda to 0xde capnn matn togn pwmn eccfn cappn 16 bit comparator match cf cr ccon 0xd8 ccf1 ccf0 pca it enable cexn pca counter/timer ?1? ?0? write to ccapnl reset write to ccapnh
112 T89C51CC02 4126f?can?12/03 figure 47. pca pwm mode cl rolls over from ffh to 00h loads ccapnh contents into ccapnl ccapnl ccapnh 8-bit comparator cl (8 bits) ?0? ?1? cl < ccapnl cl >= ccapnl cex pwmn ccapmn.1 ecomn ccapmn.6
113 T89C51CC02 4126f?can?12/03 pca registers table 94. cmod register cmod (s:d9h) pca counter mode register reset value = 0xxx x000b 76543210 cidl - - - - cps1 cps0 ecf bit number bit mnemonic description 7cidl pca counter idle control bit clear to let the pca run during idle mode. set to stop the pca when idle mode is invoked. 6- reserved the value read from this bit is indeterminate. do not set this bit. 5- reserved the value read from this bit is indeterminate. do not set this bit. 4- reserved the value read from this bit is indeterminate. do not set this bit. 3- reserved the value read from this bit is indeterminate. do not set this bit. 2-1 cps1:0 ewc count pulse select bits cps1 cps0 clock source 0 0 internal clock, fpca/6 0 1 internal clock, fpca/2 1 0 timer 0 overflow 1 1 external clock at eci/p1.2 pin (max. rate = fpca/4) 0ecf enable pca counter overflow interrupt bit clear to disable cf bit in ccon register to generate an interrupt. set to enable cf bit in ccon register to generate an interrupt.
114 T89C51CC02 4126f?can?12/03 table 95. ccon register ccon (s:d8h) pca counter control register reset value = 00xx xx00b 76543210 cf cr - - - - ccf1 ccf0 bit number bit mnemonic description 7cf pca timer/counter overflow flag set by hardware when the pca timer/counter rolls over. this generates a pca interrupt request if the ecf bit in cmod register is set. must be cleared by software. 6cr pca timer/counter run control bit clear to turn the pca timer/counter off. set to turn the pca timer/counter on. 5-2 - reserved the value read from these bist are indeterminate. do not set these bits. 1 ccf1 pca module 1 compare/capture flag set by hardware when a match or capture occurs. this generates a pca interrupt request if the eccf 1 bit in ccapm 1 register is set. must be cleared by software. 0 ccf0 pca module 0 compare/capture flag set by hardware when a match or capture occurs. this generates a pca interrupt request if the eccf 0 bit in ccapm 0 register is set. must be cleared by software.
115 T89C51CC02 4126f?can?12/03 table 96. ccapnh registers ccap0h (s:fah) ccap1h (s:fbh) pca high byte compare/capture module n register (n=0..1) reset value = 0000 0000b table 97. ccapnl registers ccap0l (s:eah) ccap1l (s:ebh) pca low byte compare/capture module n register (n=0..1) reset value = 0000 0000b 76543210 ccapnh 7 ccapnh 6 ccapnh 5 ccapnh 4 ccapnh 3 ccapnh 2 ccapnh 1 ccapnh 0 bit number bit mnemonic description 7:0 ccapnh 7:0 high byte of ewc-pca comparison or capture values 76543210 ccapnl 7 ccapnl 6 ccapnl 5 ccapnl 4 ccapnl 3 ccapnl 2 ccapnl 1 ccapnl 0 bit number bit mnemonic description 7:0 ccapnl 7:0 low byte of ewc-pca comparison or capture values
116 T89C51CC02 4126f?can?12/03 table 98. ccapmn registers ccapm0 (s:dah) ccapm1 (s:dbh) pca compare/capture module n mode registers (n=0..1) reset value = x000 0000b 76543210 - ecomn cappn capnn matn togn pwmn eccfn bit number bit mnemonic description 7- reserved the value read from this bit is indeterminate. do not set this bit. 6ecomn enable compare mode module x bit clear to disable the compare function. set to enable the compare function. the compare function is used to implement the software timer, the high-speed output, the pulse width modulator (pwm) and the watchdog timer (wdt). 5 cappn capture mode (positive) module x bit clear to disable the capture function triggered by a positive edge on cexx pin. set to enable the capture function triggered by a positive edge on cexx pin 4 capnn capture mode (negative) module x bit clear to disable the capture function triggered by a negative edge on cexx pin. set to enable the capture function triggered by a negative edge on cexx pin. 3matn match module x bit set when a match of the pca counter with the compare/capture register sets ccfx bit in ccon register, flagging an interrupt. 2 togn toggle module x bit the toggle mode is configured by setting ecomx, matx and togx bits. set when a match of the pca counter with the compare/capture register toggles the cexx pin. 1pwmn pulse width modulation module x mode bit set to configure the module x as an 8-bit pulse width modulator with output waveform on cexx pin. 0 eccfn enable ccfx interrupt bit clear to disable ccfx bit in ccon register to generate an interrupt request. set to enable ccfx bit in ccon register to generate an interrupt request.
117 T89C51CC02 4126f?can?12/03 table 99. ch register ch (s:f9h) pca counter register high value reset value = 0000 00000b table 100. cl register cl (s:e9h) pca counter register low value reset value = 0000 00000b 76543210 ch 7 ch 6 ch 5 ch 4 ch 3 ch 2 ch 1 ch 0 bit number bit mnemonic description 7:0 ch 7:0 high byte of timer/counter 76543210 cl 7 cl 6 cl 5 cl 4 cl 3 cl 2 cl 1 cl 0 bit number bit mnemonic description 7:0 cl0 7:0 low byte of timer/counter
118 T89C51CC02 4126f?can?12/03 analog-to-digital converter (adc) this section describes the on-chip 10-bit analog-to-digital converter of the T89C51CC02. eight adc channels are available for sampling of the external sources an0 to an7. an analog multiplexer allows the single adc converter to select one from the 8 adc channels as adc input voltage (adcin). adcin is converted by the 10-bit- cascaded potentiometric adc. two modes of conversion are available: - standard conversion (8 bits). - precision conversion (10 bits). for the precision conversion, set bit psidle in adcon register and start conversion. the device is in a pseudo-idle mode, the cpu does not run but the peripherals are always running. this mode allows digital noise to be as low as possible, to ensure high precision conversion. for this mode it is necessary to work with end of conversion interrupt, which is the only way to wake the device up. if another interrupt occurs during the precision conversion, it will be served only after this conversion is completed. features 8 channels with multiplexed inputs 10-bit cascaded potentiometric adc conversion time 16 micro-seconds (typ.) zero error (offset) 2 lsb max positive external reference voltage range (varef) 2.4 to 3.0-volt (typ.) adcin range 0 to 3-volt integral non-linearity typical 1 lsb, max. 2 lsb differential non-linearity typical 0.5 lsb, max. 1 lsb conversion complete flag or conversion complete interrupt selectable adc clock adc port1 i/o functions port 1 pins are general i/o that are shared with the adc channels. the channel select bit in adcf register define which adc channel/port1 pin will be used as adcin. the remaining adc channels/port1 pins can be used as general purpose i/o or as the alter- nate function that is available. a conversion launched on a channel which are not selected on adcf register will not have any effect. va ref varef should be connected to a low impedance point and must remain in the range specified varef absolute maximum range (see section ?ac-dc?). . if the adc is not used, it is recommended to tie varef to vagnd.
119 T89C51CC02 4126f?can?12/03 figure 48. adc description figure 49 shows the timing diagram of a complete conversion. for simplicity, the figure depicts the waveforms in idealized form and do not provide precise timing information. for adc characteristics and timing parameters refer to the section ?ac characteristics? of this datasheet. figure 49. timing diagram note: tsetup min, see the ac parameter for a/d conversion. tconv = 11 clock adc = 1sample and hold + 10-bit conversion the user must ensure that tsetup time between setting aden and the start of the first conversion. adc converter operation a start of single a/d conversion is triggered by setting bit adsst (adcon.3). after completion of the a/d conversion, the adsst bit is cleared by hardware. the end-of-conversion flag adeoc (adcon.4) is set when the value of conversion is available in addh and addl, it must be cleared by software. if the bit eadc (ien1.1) is set, an interrupt occur when flag adeoc is set (see figure 51). clear this flag for re- arming the interrupt. note: always leave tsetup time before starting a conversion unless aden is permanently high. in this case one should wait tsetup only before the first conversion rai an0/p1.0 an1/p1.1 an2/p1.2 an3/p1.3 an4/p1.4 an5/p1.5 an6/p1.6 an7/p1.7 000 001 010 011 100 101 110 111 sch2 adcon.2 sch0 adcon.0 sch1 adcon.1 adc clock aden adcon.5 adsst adcon.3 adeoc adcon.4 adc interrupt request eadc ien1.1 control avss sample and hold addh varef r/2r dac vagnd 8 10 + - addl 2 sar adcin cai aden adsst adeoc t setup t conv clk
120 T89C51CC02 4126f?can?12/03 the bits sch0 to sch2 in adcon register are used for the analog input channel selection. table 101. selected analog input voltage conversion when the adcin is equals to varef the adc converts the signal to 3ffh (full scale). if the input voltage equals vagnd, the adc converts it to 000h. input voltage between varef and vagnd are a straight-line linear conversion. all other voltages will result in 3ffh if greater than varef and 000h if less than vagnd. note that adcin should not exceed varef absolute maximum range (see section ?ac-dc?). clock selection the adc clock is the same as cpu. the maximum clock frequency is defined in the dc parmeter for a/d converter. a pres- caler is featured (adcclk) to generate the adc clock from the oscillator frequency. f adc = fcpu clock/ (4 (or 2 in x2 mode)* prs ) figure 50. a/d converter clock adc standby mode when the adc is not used, it is possible to set it in standby mode by clearing bit aden in adcon register. in this mode the power dissipation is reduced. it adc management an interrupt end-of-conversion will occurs when the bit adeoc is activated and the bit eadc is set. for re-arming the interrupt the bit adeoc must be cleared by software. sch2 sch1 sch0 selected analog input 000an0 001an1 010an2 011an3 100an4 101an5 110an6 111an7 prescaler adclk a/d converter adc clock cpu clock cpu core clock symbol 2
121 T89C51CC02 4126f?can?12/03 figure 51. adc interrupt structure routine examples 1. configure p1.2 and p1.3 in adc channels // configure channel p1.2 and p1.3 for adc adcf = 0ch // enable the adc adcon = 20h 2. start a standard conversion // the variable ?channel? contains the channel to convert // the variable ?value_converted? is an unsigned int // clear the field sch[2:0] adcon &= f8h // select channel adcon |= channel // start conversion in standard mode adcon |= 08h // wait flag end of conversion while((adcon & 01h)!= 01h) // clear the end of conversion flag adcon &= efh // read the value value_converted = (addh << 2)+(addl) 3. start a precision conversion (need interrupt adc) // the variable ?channel? contains the channel to convert // enable adc eadc = 1 // clear the field sch[2:0] adcon &= f8h // select the channel adcon |= channel // start conversion in precision mode adcon |= 48h note: to enable the adc interrupt: ea = 1 adeoc adcon.2 eadc ien1.1 adci
122 T89C51CC02 4126f?can?12/03 registers table 102. adcf register adcf (s:f6h) adc configuration reset value = 0000 0000b table 103. adcon register adcon (s:f3h) adc control register reset value = x000 0000b 76543210 ch 7 ch 6 ch 5 ch 4 ch 3 ch 2 ch 1 ch 0 bit number bit mnemonic description 7 - 0 ch 0:7 channel configuration set to use p1.x as adc input. clear to use p1.x as standart i/o port. 76543210 - psidle aden adeoc adsst sch2 sch1 sch0 bit number bit mnemonic description 7- reserved the value read from these bits are indeterminate. do not set these bits. 6 psidle pseudo idle mode (best precision) set to put in idle mode during conversion clear to convert without idle mode. 5aden enable/standby mode set to enable adc clear for standby mode. 4adeoc end of conversion set by hardware when adc result is ready to be read. this flag can generate an interrupt. must be cleared by software. 3 adsst start and status set to start an a/d conversion. cleared by hardware after completion of the conversion 2-0 sch2:0 selection of channel to convert see table 101
123 T89C51CC02 4126f?can?12/03 table 104. adclk register adclk (s:f2h) adc clock prescaler reset value = xxx0 0000b table 105. addh register addh (s:f5h read only) adc data high byte register reset value = 00h table 106. addl register addl (s:f4h read only) adc data low byte register reset value = 00h 76543210 - - - prs 4 prs 3 prs 2 prs 1 prs 0 bit number bit mnemonic description 7 - 5 - reserved the value read from these bits are indeterminate. do not set these bits. 4-0 prs4:0 clock prescaler fadc = fcpuclock/(4*prs)) in x1 mode fadc=fcpuclock/(2*prs) in x2 mode 76543210 adat 9 adat 8 adat 7 adat 6 adat 5 adat 4 adat 3 adat 2 bit number bit mnemonic description 7 - 0 adat9:2 adc result bits 9-2 76543210 - - - - - - adat 1 adat 0 bit number bit mnemonic description 7 - 2 - reserved the value read from these bits are indeterminate. do not set these bits. 1-0 adat1:0 adc result bits 1-0
124 T89C51CC02 4126f?can?12/03 interrupt system introduction the can controller has a total of 10 interrupt vectors: two external interrupts (int0 and int1 ), three timer interrupts (timers 0, 1 and 2), a serial port interrupt, a pca, a can interrupt, a timer overrun interrupt and an adc. these interrupts are shown below. figure 52. interrupt control system ecan ien1.0 ex0 ien0.0 00 01 10 11 external interrupt 0 int0# ea ien0.7 ex1 ien0.2 external interrupt 1 int1# et0 ien0.1 timer 0 ec ien0.6 pca et1 ien0.3 timer 1 es ien0.4 uart eadc ien1.1 a to d converter etim ien1.2 can timer can interrupt enable lowest priority interrupts highest priority enable 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 priority interrup ts txdc rxdc ain1:0 iph/l controller timer 2 00 01 10 11 et2 ien0.5 txd rxd cex0:1
125 T89C51CC02 4126f?can?12/03 each of the interrupt sources can be individually enabled or disabled by setting or clear- ing a bit in the interrupt enable register. this register also contains a global disable bit which must be cleared to disable all the interrupts at the same time. each interrupt source can also be individually programmed to one of four priority levels by setting or clearing a bit in the interrupt priority registers. the table below shows the bit values and priority levels associated with each combination. table 107. priority level bit values a low-priority interrupt can be interrupted by a high priority interrupt but not by another low-priority interrupt. a high-priority interrupt cannot be interrupted by any other interrupt source. if two interrupt requests of different priority levels are received simultaneously, the request of the higher priority level is serviced. if interrupt requests of the same priority level are received simultaneously, an internal polling sequence determines which request is serviced. thus within each priority level there is a second priority structure determined by th e polling sequence, see table 108. table 108. interrupt priority within level iph.x ipl.x interrupt level priority 0 0 0 (lowest) 011 102 113 (highest) interrupt name interrupt address vector interrupt number polling priority external interrupt (int0) 0003h 1 1 timer0 (tf0) 000bh 2 2 external interrupt (int1) 0013h 3 3 timer 1 (tf1) 001bh 4 4 pca (cf or ccfn) 0033h 7 5 uart (ri or ti) 0023h 5 6 timer 2 (tf2) 002bh 6 7 can (txok, rxok, err or ovrbuf) 003bh 8 8 adc (adci) 0043h 9 9 can timer overflow (ovrtim) 004bh 10 10
126 T89C51CC02 4126f?can?12/03 registers figure 53. ien0 register ien0 (s:a8h) interrupt enable register reset value = 0000 0000b bit addressable 76543210 ea ec et2 es et1 ex1 et0 ex0 bit number bit mnemonic description 7ea enable all interrupt bit clear to disable all interrupts. set to enable all interrupts. if ea=1, each interrupt source is individually enabled or disabled by setting or clearing its interrupt enable bit. 6ec pca interrupt enable clear to disable the pca interrupt. set to enable the pca interrupt. 5et2 timer 2 overflow interrupt enable bit clear to disable timer 2 overflow interrupt. set to enable timer 2 overflow interrupt. 4es serial port enable bit clear to disable serial port interrupt. set to enable serial port interrupt. 3et1 timer 1 overflow interrupt enable bit clear to disable timer 1 overflow interrupt. set to enable timer 1 overflow interrupt. 2ex1 external interrupt 1 enable bit clear to disable external interrupt 1. set to enable external interrupt 1. 1et0 timer 0 overflow interrupt enable bit clear to disable timer 0 overflow interrupt. set to enable timer 0 overflow interrupt. 0ex0 external interrupt 0 enable bit clear to disable external interrupt 0. set to enable external interrupt 0.
127 T89C51CC02 4126f?can?12/03 figure 54. ien1 register ien1 (s:e8h) interrupt enable register reset value = xxxx x000b bit addressable 76543210 - - - - etim eadc ecan bit number bit mnemonic description 7- reserved the value read from this bit is indeterminate. do not set this bit. 6- reserved the value read from this bit is indeterminate. do not set this bit. 5- reserved the value read from this bit is indeterminate. do not set this bit. 4- reserved the value read from this bit is indeterminate. do not set this bit. 3- reserved the value read from this bit is indeterminate. do not set this bit. 2etim timer overrun interrupt enable bit clear to disable the timer overrun interrupt. set to enable the timer overrun interrupt. 1 eadc adc interrupt enable bit clear to disable the adc interrupt. set to enable the adc interrupt. 0ecan can interrupt enable bit clear to disable the can interrupt. set to enable the can interrupt.
128 T89C51CC02 4126f?can?12/03 table 109. ipl0 register ipl0 (s:b8h) interrupt enable register reset value = x000 0000b bit addressable 76543210 - ppc pt2 ps pt1 px1 pt0 px0 bit number bit mnemonic description 7- reserved the value read from this bit is indeterminate. do not set this bit. 6 ppc pca interrupt priority bit refer to ppch for priority level 5pt2 timer 2 overflow interrupt priority bit refer to pt2h for priority level. 4ps serial port priority bit refer to psh for priority level. 3pt1 timer 1 overflow interrupt priority bit refer to pt1h for priority level. 2px1 external interrupt 1 priority bit refer to px1h for priority level. 1pt0 timer 0 overflow interrupt priority bit refer to pt0h for priority level. 0px0 external interrupt 0 priority bit refer to px0h for priority level.
129 T89C51CC02 4126f?can?12/03 table 110. ipl1 register ipl1 (s:f8h) interrupt priority low register 1 reset value = xxxx x 000b bit addressable 76543210 - - - - povrl padcl pcanl bit number bit mnemonic description 7- reserved the value read from this bit is indeterminate. do not set this bit. 6- reserved the value read from this bit is indeterminate. do not set this bit. 5- reserved the value read from this bit is indeterminate. do not set this bit. 4- reserved the value read from this bit is indeterminate. do not set this bit. 3- reserved the value read from this bit is indeterminate. do not set this bit. 2povrl timer overrun interrupt priority level less significant bit refer to pi2ch for priority level. 1 padcl adc interrupt priority level less significant bit refer to pspih for priority level. 0 pcanl can interrupt priority level less significant bit refer to pkbh for priority level.
130 T89C51CC02 4126f?can?12/03 table 111. iph0 register iph0 (b7h) interrupt high priority register reset value = x000 0000b 76543210 - ppch pt2h psh pt1h px1h pt0h px0h bit number bit mnemonic description 7- reserved the value read from this bit is indeterminate. do not set this bit. 6 ppch pca interrupt priority level most significant bit ppch ppc priority level 00lowest 01 10 1 1 highest priority 5pt2h timer 2 overflow interrupt high priority bit pt2h pt2 priority level 00lowest 01 10 1 1 highest 4 psh serial port high priority bit psh ps priority level 00lowest 01 10 1 1 highest 3pt1h timer 1 overflow interrupt high priority bit pt1h pt1 priority level 00lowest 01 10 1 1 highest 2px1h external interrupt 1 high priority bit px1h px1 priority level 00lowest 01 10 1 1 highest 1pt0h timer 0 overflow interrupt high priority bit pt0h pt0 priority level 00lowest 01 10 1 1 highest 0px0h external interrupt 0 high priority bit px0h px0 priority level 00lowest 01 10 1 1 highest
131 T89C51CC02 4126f?can?12/03 table 112. iph1 register iph1 (s:f7h) interrupt high priority register 1 reset value = xxxx x000b 76543210 - - - - povrh padch pcanh bit number bit mnemonic description 7- reserved the value read from this bit is indeterminate. do not set this bit. 6- reserved the value read from this bit is indeterminate. do not set this bit. 5- reserved the value read from this bit is indeterminate. do not set this bit. 4- reserved the value read from this bit is indeterminate. do not set this bit. 3- reserved the value read from this bit is indeterminate. do not set this bit. 2povrh timer overrun interrupt priority level most significant bit povrh povrl priority level 00lowest 01 10 1 1 highest 1 padch adc interrupt priority level most significant bit padch padcl priority level 00lowest 01 10 1 1 highest 0 pcanh can interrupt priority level most significant bit pcanh pcanl priority level 00lowest 01 10 1 1 highest
132 T89C51CC02 4126f?can?12/03 electrical characteristics dc parameters for standard voltage t a = -40 c to +85 c; v ss = 0 v; v cc = 3 volts to 5.5 volts; f = 0 to 40 mhz notes: 1. typicals are based on a limited number of samples and are not guaranteed. the values listed are at room temperature. 2. flash retention is guaranteed with the same formula for v cc min down to 0v. 3. under steady state (non-transient) conditions, i ol must be externally limited as follows: maximum i ol per port pin: 10 ma absolute maximum ratings i = industrial ....................................................... -40 c to 85 c storage temperature ................................... -65 c to + 150 c voltage on v cc from v ss .....................................-0.5v to + 6v voltage on any pin from v ss .....................-0.5v to v cc + 0.2v power dissipation ............................................................. 1 w note: s tresses at or above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other condi- tions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions may affect device reliability. power dissipation value is based on the maximum allowable die temperature and the thermal resistance of the package. table 113. dc parameters in standard voltage symbol parameter min typ (1) max unit test conditions v il input low voltage -0.5 0.2vcc - 0.1 v v ih input high voltage except xtal1, rst 0.2 v cc + 0.9 v cc + 0.5 v v ih1 (2) input high voltage, xtal1, rst 0.7 v cc v cc + 0.5 v v ol output low voltage, ports 1, 2, 3 and 4 (3) 0.3 0.45 1.0 v v v i ol = 100 a i ol = 1.6 ma i ol = 3.5 ma v oh output high voltage, ports 1, 2, 3, 4 and 5 v cc - 0.3 v cc - 0.7 v cc - 1.5 v v v i oh = -10 a i oh = -30 a i oh = -60 a v cc = 5v 10% r rst rst pulldown resistor 50 90 200 k ? i il logical 0 input current ports 1, 2, 3 and 4 -50 a vin = 0.45v i li input leakage current 10 a0.45v < vin < v cc i tl logical 1 to 0 transition current, ports 1, 2, 3 and 4 -650 a vin = 2.0v c io capacitance of i/o buffer 10 pf fc = 1 mhz t a = 25 c i pd power-down current 160 400 a3v < v cc < 5.5v (4) i cc power supply current i ccop (6) = 0.7 freq (mhz) + 3 ma i ccidle (5) = 0.6 freq (mhz) + 2 ma
133 T89C51CC02 4126f?can?12/03 maximum i ol per 8-bit port: ports 1, 2 and 3: 15 ma maximum total i ol for all output pins: 71 ma if i ol exceeds the test condition, v ol may exceed the related specification. pins are not guaranteed to sink current greater than the listed test conditions. 4. power-down i cc is measured with all output pins disconnected; xtal2 nc.; rst = v ss (see figure 57.). 5. idle i cc is measured with all output pins disconnected; xtal1 driven with t clch , t chcl = 5 ns, v il = v ss + 0.5v, v ih = v cc - 0.5v; xtal2 n.c; rst = v ss (see figure 56.). 6. operating i cc is measured with all output pins disconnected; xtal1 driven with t clch , t chcl = 5 ns (see figure 58.), v il = v ss + 0.5v, v ih = v cc - 0.5v; xtal2 n.c.; rst = v cc . i cc would be slightly higher if a crystal oscillator used (see figure 55.). figure 55. i cc test condition, active mode figure 56. i cc test condition, idle mode va vc c v cc i cc (nc) clock signal v cc all other pins are disconnecte d. rst xtal2 xtal1 v ss v cc vagnd rst xtal2 xtal1 v cc i cc (nc) vavcc v cc all other pins are disconnecte d. clock signal v ss va gnd
134 T89C51CC02 4126f?can?12/03 figure 57. i cc test condition, power-down mode figure 58. clock signal waveform for i cc tests in active and idle modes dc parameters for a/d converter table 114. dc parameters for ad converter in precision conversion notes: 1. typicals are based on a limited number of samples and are not guaranteed. 2. with adc enabled. vavcc rst xtal2 xtal1 v ss v cc i cc (nc) v cc all other pins are disconnected. vagnd v cc -0.5v 0.45v 0.7v cc 0.2v cc -0.1 t clch t chcl t clch = t chcl = 5ns. symbol parameter min typ (1) max unit test conditions avin analog input voltage vss- 0.2 max vref + 0.6 v vavcc analog supply voltage vref vcc vcc + 10% v rref (2) resistance between varef and vss 12 16 24 k ? varef reference voltage 2.40 3.00 v cai analog input capacitance 60 pf during sampling rai analog input resistor 400 ? during sampling inl integral non linearity 1 2 lsb dnl differential non linearity 0.5 1 lsb oe offset error -2 2 lsb
135 T89C51CC02 4126f?can?12/03 ac parameters serial port timing - shift register mode table 115. symbol description (f = 40 mhz) table 117. ac parameters for a variable clock symbol parameter t xlxl serial port clock cycle time t qvhx output data set-up to clock rising edge t xhqx output data hold after clock rising edge t xhdx input data hold after clock rising edge t xhdv clock rising edge to input data valid table 116. ac parameters for a fix clock (f = 40 mhz) symbol min max units t xlxl 300 ns t qvhx 200 ns t xhqx 30 ns t xhdx 0ns t xhdv 117 ns symbol type standard clock x2 clock x parameter for -m range units t xlxl min 12 t 6 t ns t qvhx min 10 t - x 5 t - x 50 ns t xhqx min 2 t - x t - x 20 ns t xhdx min x x 0 ns t xhdv max 10 t - x 5 t- x 133 ns
136 T89C51CC02 4126f?can?12/03 shift register timing waveforms external clock drive characteristics (xtal1) table 118. ac parameters external clock drive waveforms ac testing input/output waveforms ac inputs during testing are driven at v cc - 0.5 for a logic ?1? and 0.45v for a logic ?0?. timing measurement are made at v ih min for a logic ?1? and v il max for a logic ?0?. float waveforms valid valid valid valid valid valid input data va lid 0123456 8 7 clock output data write to sbuf clear ri t xlxl t qvxh t xhqx t xhdv t xhdx set ti set ri instruction 01234567 valid symbol parameter min max units t clcl oscillator period 25 ns t chcx high time 5 ns t clcx low time 5 ns t clch rise time 5 ns t chcl fall time 5 ns t chcx /t clcx cyclic ratio in x2 mode 40 60 % v cc -0.5v 0.45v 0.7v cc 0.2v cc -0.1 t chcl t clcx t clcl t clch t chcx input/output 0.2 v cc + 0.9 0.2 v cc - 0.1 v cc -0.5v 0.45 v float v oh - 0.1v v ol + 0.1v v load v load + 0.1v v load - 0.1v
137 T89C51CC02 4126f?can?12/03 for timing purposes as port pin is no longer floating when a 100 mv change from load voltage occurs and begins to float when a 100 mv change from the loaded v oh /v ol level occurs. i ol /i oh 20ma. clock waveforms valid in normal clock mode. in x2 mode xtal2 must be changed to xtal2/2. flash memory table 119. memory ac timing v cc = 3.0v to 5.5v, t a = -40 c to +85 c figure 59. flash memory - internal busy waveforms a/d converter table 120. ac parameters for a/d conversion symbol parameter min typ max unit t bhbl flash internal busy (programming) time 13 17 ms n fcy number of flash erase/write cycles 100 000 cycles t fdr flash data retention time 10 years fbusy bit t bhbl symbol parameter min typ max unit t setup 4s adc clock frequency 700 khz
138 T89C51CC02 4126f?can?12/03 ordering information factory default programming for T89C51CC02ca-xxxx is bootloader can and hsb = bbh: x1 mode bljb = 0 : jump to bootloader lb2 = 0 : security level 3. (1) factory default programming for T89C51CC02ua-xxxx is bootloader uart and hsb = bbh: x1 mode bljb = 0 : jump to bootloader lb2 = 0 : security level 3. (1) notes: 1. lb2 = 0 is not described in table 22 program load bit. lb2 = 0 is equivalent to lb1 = 0: security level 3. 2. customer can change these modes by re-programming with a parallel programmer, this can be done by an atmel distributor. part number bootloader temperature range package packing product marking T89C51CC02ca-ratim can (2) industrial vqfp32 tray 89c51cc02ca-im T89C51CC02ca-sisim can (2) industrial plcc28 stick 89c51cc02ca-im T89C51CC02ca-tdsim can (2) industrial soic24 stick 89c51cc02ca-im T89C51CC02ca-tisim can (2) industrial soic28 stick 89c51cc02ca-im T89C51CC02ua-ratim uart (2) industrial vqfp32 tray 89c51cc02ua-im T89C51CC02ua-sisim uart (2) industrial plcc28 stick 89c51cc02ua-im T89C51CC02ua-tdsim uart (2) industrial soic24 stick 89c51cc02ua-im T89C51CC02ua-tisim uart (2) industrial soic28 stick 89c51cc02ua-im
139 T89C51CC02 4126f?can?12/03 package drawings vqfp32
140 T89C51CC02 4126f?can?12/03 plcc28
141 T89C51CC02 4126f?can?12/03 soic24
142 T89C51CC02 4126f?can?12/03 soic28
143 T89C51CC02 4126f?can?12/03 datasheet change log for T89C51CC02 changes from 4126c- 10/02 to 4126d-04/03 1. changed the endurance of flash to 100, 000 write/erase cycles. 2. added note on flash retention formula for v ih1 , in section "dc parameters for standard voltage", page 141.changes from 4129f-11/02 to 4129g-04/03 1. changed the endurance of flash to 100, 000 write/erase cycles. 2. added note on flash retention formula for v ih1 , in section "dc parameters for standard voltage", page 141. changes from 4126d- 05/03 to 4126e - 10/03 1. updated ?electrical characteristics? on page 132. 2. corrected figure 35 on page 75. changes from 4126e - 10/03 to 4126f - 12/03 1. changed value of ipdmax to 400, section "absolute maximum ratings", page 132. 2. pca , cps0, register correction, section "pca registers", page 113. 3. cross memory section added. section "operation cross memory access", page 42.
table of contents i table of contents features ................................................................................................. 1 description ............................................................................................ 2 block diagram ....................................................................................... 2 pin configurations ................................................................................ 3 pin description...................................................................................... 5 i/o configurations ................................................................................................. 7 port structure ....................................................................................................... 7 read-modify-write instructions ............................................................................ 8 quasi bi-directional port operation...................................................................... 8 sfr mapping ....................................................................................... 10 clock .................................................................................................... 16 description ......................................................................................................... 16 register .............................................................................................................. 19 power management ............................................................................ 20 reset pin .............................................................................................. 20 at power-up (cold reset)..................................................................................... 20 during a normal operation (warm reset) ......................................................... 21 watchdog reset................................................................................................. 21 reset recommendation to prevent flash corruption......................................... 22 idle mode............................................................................................................ 22 power-down mode ............................................................................................. 22 registers ............................................................................................................. 24 data memory ....................................................................................... 25 internal space .................................................................................................... 25 dual data pointer ............................................................................................... 27 registers ............................................................................................................ 28 eeprom data memory ....................................................................... 30 write data in the column latches...................................................................... 30 programming...................................................................................................... 30 read data .......................................................................................................... 30 examples............................................................................................................ 31 registers ............................................................................................................ 32
ii program/code memory ...................................................................... 33 flash memory architecture ................................................................................ 33 overview of fm0 operations.............................................................................. 35 registers ............................................................................................................ 41 operation cross memory access ..................................................... 42 sharing instructions ........................................................................... 43 in-system programming (isp) ........................................................... 45 flash programming and erasure ....................................................................... 45 boot process ...................................................................................................... 46 application-programming-interface.................................................................... 46 xrow bytes ...................................................................................................... 47 hardware conditions.......................................................................................... 47 hardware security byte...................................................................................... 48 serial i/o port ...................................................................................... 49 framing error detection .................................................................................... 49 automatic address recognition ......................................................................... 50 given address.................................................................................................... 50 broadcast address ............................................................................................. 51 registers ............................................................................................................. 52 timers/counters ................................................................................. 55 timer/counter operations.................................................................................. 55 timer 0 ............................................................................................................... 55 timer 1 ............................................................................................................... 57 interrupt .............................................................................................................. 58 registers ............................................................................................................ 59 timer 2 ................................................................................................. 62 auto-reload mode ............................................................................................. 62 programmable clock-output.............................................................................. 63 registers ............................................................................................................ 64 watchdog timer .................................................................................. 67 watchdog programming...................................................................................... 68 watchdog timer during power-down mode and idle ...................... 69 register .............................................................................................................. 69 can controller .................................................................................... 71
table of contents iii can controller description ................................................................................ 71 can controller mailbox and registers organization ......................................... 72 can controller management ............................................................. 73 it can management.......................................................................................... 74 bit timing and baud rate................................................................................... 76 fault confinement .............................................................................................. 78 acceptance filter................................................................................................ 79 data and remote frame .................................................................................... 80 time trigger communication (ttc) and message stamping ............................ 81 can autobaud and listening mode ................................................................... 82 routine examples .............................................................................................. 82 can sfrs.......................................................................................................... 85 registers ............................................................................................................ 86 programmable counter array (pca) ............................................... 106 pca timer........................................................................................................ 106 pca modules ................................................................................................... 108 pca interrupt.................................................................................................... 109 pca capture mode .......................................................................................... 109 16-bit software timer mode ............................................................................. 110 high speed output mode................................................................................. 111 pulse width modulator mode ........................................................................... 111 pca registers.................................................................................................. 113 analog-to-digital converter (adc) .................................................. 118 features ........................................................................................................... 118 adc port1 i/o functions.................................................................................. 118 varef ............................................................................................................. 118 adc converter operation ................................................................................ 119 voltage conversion .......................................................................................... 120 clock selection................................................................................................. 120 adc standby mode.......................................................................................... 120 it adc management........................................................................................ 120 routine examples ............................................................................................ 121 registers ........................................................................................................... 122 interrupt system ............................................................................... 124 introduction....................................................................................................... 124 registers .......................................................................................................... 126 electrical characteristics ................................................................. 132 absolute maximum ratings.............................................................................. 132
iv dc parameters for standard voltage............................................................... 132 dc parameters for a/d converter.................................................................... 134 ac parameters................................................................................................. 135 ordering information ........................................................................ 138 package drawings ............................................................................ 139 vqfp32............................................................................................................ 139 plcc28............................................................................................................ 140 soic24............................................................................................................. 141 soic28............................................................................................................. 142 datasheet change log for T89C51CC02 ........................................ 143 changes from 4126c - 10/02 to 4126d - 04/03 ............................................... 143 changes from 4126d - 05/03 to 4126e - 10/03 ............................................... 143 changes from 4126e - 10/03 to 4126f - 12/03................................................ 143 table of contents ................................................................................... i
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